Programmable delay clock buffer

Details Programmable delay clock buffer Programmable delay clock buffer

2007-07-23

2010-12-07

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S401000, C713S600000, C711S105000, C711S111000, C375S354000, C327S146000, C327S155000, C327S243000, C327S291000

Reexamination Certificate

active

07849348

ABSTRACT:
A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.

REFERENCES:
patent: 5712583 (1998-01-01), Frankeny
patent: 6535043 (2003-03-01), Chen
patent: 7065666 (2006-06-01), Janzen
patent: 7233170 (2007-06-01), Becker et al.
U.S. Appl. No. 12/728,101, filed Mar. 19, 2010, Loinaz, Marc J.
U.S. Appl. No. 12/728,113, filed Mar. 19, 2010, Loinaz et al.

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