Programmable current source

Details Programmable current source Programmable current source

1999-10-18

2001-02-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S210130

Reexamination Certificate

active

06185130

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to a programmable current source and more specifically to a programmable current source that generates reference current through bit lines of a memory array.
RELATED ART
FIG. 1
illustrates a cross sectional view of a conventional memory transistor, also known as a memory cell. The memory transistor includes a control gate CG, a floating gate FG, a drain D, a source S, and a well W. Thin oxide layers isolate the floating gate FG from the control gate CG as well as the well W.
FIG. 2
schematically illustrates a conventional NAND type flash memory array
100
that includes numerous memory cells, each depicted in
FIG. 1. A
“string” includes a selection transistor T
i-1
, memory transistors M
i-1
to M
i-j
, and a selection transistor T
i-2
, all being serially coupled. Each string can be coupled to a bit line BLj and a common source CS through selection transistors T
i-1
and T
i-2
, respectively. The control gates for selection transistors T
i-1
and T
i-2
are respectively connected to selection lines Sl
1
and Sl
2
. The control gates for the memory transistors M
i-1
to M
i-j
are respectively connected to word lines W
1
to W
j
. Typically, a read operation is performed on a page basis, i.e., flash memory cells coupled to a word line are read together.
Herein, a memory transistor represents logical LOW when it is programmed to have a threshold voltage that is larger than a predetermined minimum threshold voltage for logical LOW bits. Correspondingly, a memory transistor represents a logical HIGH when it is erased to have a threshold voltage that is less than a predetermined maximum threshold voltage for logical HIGH bits. One skilled in the art will understand that logic level assignments to the predetermined minimum and maximum threshold voltages are arbitrary.
A large variation in the programming and erasing characteristics of individual NAND type flash memory transistors among a memory array is common. The variations can be due to structural differences, which cause difference in threshold voltage characteristics. Such variations introduce differences in programming and erasing speeds among memory transistors.
After program and erase operations, a reference current is provided through each bitline BL
j
(
FIG. 2
) to determine whether the program and erase operation successful completed. Because of the variation in realized memory arrays, different reference currents may be needed for each realized memory array. Thus what is needed is a method and apparatus to determine and apply a suitable reference current.
SUMMARY
An embodiment of the present invention includes a programmable current source that provides current to a bit line coupled to a memory cell, the current source including a source of a reference current value and a reference current source that provides a reference current specified by the reference current value.
Advantageously, the programmable reference current source is used to both determine an optimal reference current level and subsequently apply the optimal reference current. Thus, an optimal reference current level can be quickly determined. In one embodiment, the level of optimal reference current is stored and used to generate the optimal reference current.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.


REFERENCES:
patent: 5822250 (1998-10-01), Krzentz
patent: 5867427 (1999-02-01), Sato
patent: 5898617 (1999-04-01), Bushey et al.
patent: 5966330 (1999-10-01), Tang et al.

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