Programmable counters for setting bus arbitration delays...

Details Programmable counters for setting bus arbitration delays... Programmable counters for setting bus arbitration delays...

2005-08-23

2005-08-23

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Counting, scheduling, or event timing

C713S600000

Reexamination Certificate

active

06934871

ABSTRACT:
A method and apparatus for generating a delay in the timing of a bus or other logic circuit such that changes may be made to timing parameters without undue hardware design changes is disclosed. A counter is used to count a number of clock cycles to time the delay. The number of clock cycles is pre-loaded into the counter from a memory. This eliminates the need for costly hardware design changes when timing parameters change, since all that must be changed is the number of clock cycles to be counted, which can be modified by replacing or reprogramming the memory.

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Chang et al., “A 723-MHz 17.2-mW CMOS Programmable Counter”, IEEE Journal of Solid-State Circuits, vol. 33, No. 10, Oct., 1998, pp 1572-1575.

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