Programmable controller with sub-phase clocking scheme

Details Programmable controller with sub-phase clocking scheme Programmable controller with sub-phase clocking scheme

2005-12-27

2005-12-27

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C326S093000, C326S096000

Reexamination Certificate

active

06981167

ABSTRACT:
A parallel processor with a built-in sub-phase clocking scheme is provided to execute sequentially executed programmable logic controller (PLC) programs in a parallel method. A translator program will translate the PLC logic design from a coding language into Electronic Design Interchange Format and that will be eventually converted to a hardware or software embodiment of the logic. The processor provides a plurality of sub-phase clock periods. The translator assigns to the same sub-phase period program elements that process their tasks in the same range of time. The elements are grouped into sub-phase so that logic elements are performed lock-step to ensure that downstream element are performed at a time when they have valid values at their inputs. The processor consequently avoids race conditions in the system and allows the parallel execution speedup of programs written for a sequential machine such as a PLC.

REFERENCES:
patent: 5210700 (1993-05-01), Tom
patent: 5978571 (1999-11-01), Grundmann
patent: 6584597 (2003-06-01), Kishinevsky et al.
patent: 2002/0091983 (2002-07-01), Andreev et al.

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