Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
2002-01-25
2004-03-30
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S020000, C700S001000, C700S002000, C700S007000, C700S011000, C700S018000, C700S020000, C709S201000, C711S166000, C712S220000, C712S225000, C713S300000, C713S324000, C714S023000
Reexamination Certificate
active
06714996
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a programmable controller system and a reset controlling method for the programmable controller system.
BACKGROUND ART
A conventional programmable controller system will be explained with reference to FIG.
7
. This programmable controller system is provided with a power-supply unit
500
for supplying power to the system, a CPU unit
510
which forms a center of the system for executing the operation processing for the control, an output unit
520
for outputting ON/OFF information to an external apparatus
600
based upon an instruction outputted by a CPU unit
510
, a data link unit
530
for executing data communication between systems (affiliated stations
610
) through dedicated lines and a positioning unit
540
connected to a servo-motor
620
for carrying out a positioning control. These units are attached to a mother board
550
containing a system bus (hereinafter, referred to as a base unit), that is, bus-connected.
In the explanation that follows, the output unit
520
, the data link unit
530
, etc., which are controlled by the CPU unit
510
, are generally referred to as an I/O unit.
The CPU unit
510
is provided with a reset circuit
512
in addition to the microprocessor (MPU)
511
. The reset circuit
512
unifies an error signal for preliminarily informing the power-supply down sent from the power supply system (power-supply reset signal: hereinafter, referred to as &Sgr;REL signal) and an error signal (hereinafter, referred to as CPUERRL signal) due to an operation error, etc., generated by the microprocessor
511
so that a reset signal (hereinafter, &Sgr;MRE signal) for controlling the resetting operation with respect to the I/O unit of the programmable controller system is outputted.
When both of the &Sgr;REL signal and the CRUERRL signal are non-active (H-level) in the reset circuit
512
, since no currents are allowed to flow through the diodes
513
and
514
, the base electric potential of the transistor
515
is set to the High level, thereby allowing a current to flow through the emitter and collector of the transistor
515
so that the &Sgr;MRE signal is set to the L level (non-active).
For example, when the power-supply unit
500
, which has detected the power-supply down due to the power supply off, outputs the &Sgr;REL signal in the L-level, a current flows in the forward direction through the diode
513
, thereby setting the base electric potential of the transistor
515
to the L-level, stopping the current to flow between the emitter and collector of the transistor
515
, and setting the &Sgr;MRE signal to the H-level (active) correspondingly.
Moreover, in the event of an operation error in the MPU
511
, the CPU unit
510
outputs the CPUERRL signal in the L-level so as to reset the I/O unit to the initial state. When the CPUERRL signal is set to the L-level, a current is allowed to flow in the forward direction of the diode
514
, thereby setting the base electric potential of the transistor
515
to the L-level, with the result that no current is allowed to flow between the emitter and collector of the transistor
515
and the &Sgr;MRE signal is set to the H-level (active).
In such a case when an operation error occurs in the MPU
511
inside the CPU
510
, by a resetting control of the MPU
511
for setting the CPUERRL signal to the L-level so as to set the I/O unit in the initial state, or by the power-supply ON/OFF operation and the resulting reset control in which the power-supply unit
500
has set the &Sgr;REL to the L-level thereby setting the I/O unit in the initial state, the &Sgr;MRE signal is transmitted to all the units (the output unit
520
, data link unit
530
, and positioning unit
540
) through the base unit
550
.
Upon receipt of the &Sgr;MRE signal of the H-level, the output unit
520
clears the latch of the output section
521
, thereby turning the external apparatus
600
off. The data link unit
530
inputs signals of H-level to the RESET terminals of the control section
531
and the transfer I/F section
532
so that the control section
531
and the transfer I/F section
532
are reset to the initial state, thereby disconnecting the network.
The positioning unit
540
resets the control section
541
to the initial state by inputting signals of H-level to the RESET terminal of the control section
541
and the CLR terminal of the output section
542
, and also clears the latch of the output section
542
so as to stop the driving operation of the servo motor
620
.
In the conventional programmable controller system as described above, since the resetting system is limited to one system, the resetting control is available only as to whether or not the entire system is reset, and it is not possible to individually reset each unit.
Moreover, in the conventional programmable controller system, when an attempt is made to reset each unit individually, the same circuits as the reset circuit
512
the number of which is as many as the number of the respective units need to be installed in the CPU unit
510
and reset signals corresponding to &Sgr;MRE the number of which is the same as the number of the units need to be provided in the inside of the CPU unit
510
and the base unit
550
; however, in the programmable controller system in which the number of units to be connected are freely determined by the user, from a realistic point of view, it is impossible to install those many circuits and control signals.
Moreover, with respect to the conventional programmable controller system, when the control section
541
of the positioning unit
540
is driven out of control, the CPU unit
510
issues a reset signal by outputting the CPUERRL signal in the L-level in order to initialize the control section
541
of the positioning unit
540
, and this case causes a problem in which the data link unit
530
is further reset to cut off the net work, etc., and the resulting problem is that the system management becomes ineffective.
Moreover, in the conventional programmable controller system, when the system is stopped due to an operation error, etc., inside the CPU unit
510
, a resetting signal is issued so as to clear the output, and this case causes a problem in which the data link unit
530
is further reset to cut off the net work, etc., and the resulting problem is that the system management becomes ineffective.
Furthermore, in the conventional programmable controller system, since each unit is not reset individually, the resulting problem is that it is not possible to control the system by altering the number of units of the CPU units
510
to a single or a plural number by using a programmable controller system using the same base unit
550
.
Therefore, in a programmable controller system using the same base unit, the objective of the present invention is to provide a programmable controller system which makes it possible to reset-control individual I/O units by using a single CPU unit or a plurality of CPU units.
DISCLOSURE OF THE INVENTION
The present invention relates to a reset controlling method of a programmable controller system which is provided with a single or a plurality of CPU units for carrying out the control of the entire system and a plurality of I/O units that are operated under a control of the CPU units, and in such are set controlling method, the CPU unit writes a command for instructing a control CPU specified information for each I/O unit, each I/O unit decodes a command instructed by the CPU unit so as to determine whether or not it is information specified by the control CPU, and holds the corresponding information specified by the control CPU in the I/O unit, the CPU units issue commands for instructing the reset control to all the I/O units, and each I/O unit decodes the command instructing its reset control, and when it has determined that the corresponding command is instructed from the CPU unit of the controlling end, it follows the reset controlling instruction so that the resetting operation of the specific I/O unit on the system specified
Gaffin Jeffrey
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tanh
Sughrue & Mion, PLLC
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