Programmable controller

Details Programmable controller Programmable controller

2006-07-11

2006-07-11

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

07076641

ABSTRACT:
When a decoding circuit (22a) decodes an instruction code stored in a pipeline register (21d), the decoding circuit (22a) decodes the device address. Based on this, it is decided which one of the device information of a RAM (11) and a RAM (12) is to be used. When the area of the RAM (12) has been assigned, the decoding circuit (22a) outputs a signal showing that the number of stop of pipeline processing is 0, unlike the assignment of the RAM (11). Therefore, a pipeline register section (21) does not set the pipeline stop signal to 1. Consequently, the reading of the instruction code from the RAM (11) and the pipeline processing are not interrupted. As a result, it is possible to realize a structure in which execution of a high-speed processing is possible and a compact/low-cost structure in the same hardware.

REFERENCES:
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patent: 5889669 (1999-03-01), Kagami et al.
patent: 6021459 (2000-02-01), Norman et al.
patent: 7-92902 (1995-04-01), None
patent: 9-23307 (1997-01-01), None
patent: 10-198409 (1998-07-01), None

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