Programmable control block for dual port SRAM application

Details Programmable control block for dual port SRAM application Programmable control block for dual port SRAM application

2011-03-29

2011-03-29

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S210100, C365S233110

Reexamination Certificate

active

07916563

ABSTRACT:
A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.

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