Programmable clock signal generation circuits and methods...

Details Programmable clock signal generation circuits and methods... Programmable clock signal generation circuits and methods...

1999-05-21

2001-03-20

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C331S057000

Reexamination Certificate

active

06204694

ABSTRACT:

This invention relates to programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals, and especially to programmable clock signal generation circuits suitable for generation of clock signals for testing integrated circuits (ICs), especially application-specific ICs (ASICs) in which logic circuits are designed using a hardware description language (HDL), synthesized into logic gates, and automatically arranged in a layout to form an ASIC's physical design.
BACKGROUND OF THE INVENTION
When testing high speed Integrated Circuits (ICs), it is desirable to test them using signals whose frequencies are equal to the specified operating frequencies of the IC. Built-In Self-Test (BIST), which requires supplying on-chip generated patterns to a Circuit Under Test (CUT), is often able to generate signals at the required frequencies using only a master clock signal supplied to the IC at the appropriate frequency. However, generating even one high frequency clock for a high speed IC is difficult if the Automatic Test Equipment (ATE) testing the IC does not have a frequency range high enough. Some manufacturers place crystal oscillator on the ATE interface board to generate the high frequency clock (e.g. 50 to 200 MHz). However, this is not a general solution, especially for application-specific ICs (ASICs) in which logic circuits are designed using a hardware description language (HDL), synthesized into logic gates, and automatically arranged in a layout to form an ASIC's physical design. The crystal oscillator must be changed for each ASIC type tested, and several crystal oscillators may be required for a single ASIC.
For many years, designers have incorporated ring oscillators into IC designs to generate periodic signals. A ring oscillator of a basic design comprises an odd-number of inverting delay elements
12
connected in series to form a ring
10
, as shown in FIG.
1
. By using a control signal ENABLE
13
, a reset logic gate
11
allows the oscillation to be stopped in a pre-determined state to have power, and allows controlled start-up of oscillation. The fewer the number of logic gates
11
,
12
, the higher the oscillation frequency of the output clock signal
14
, but three is the minimum. The output of a single inverting gate whose output is connected to its input will simply settle to a stable DC voltage mid-way between logic 1 and logic 0.
When the delay elements
12
in a ring oscillator are simple loci inverters as shown in
FIG. 1
, the oscillation frequency is dependent on temperature, power supply voltage, and variations in the IC manufacturing process. For this reason, digital ring oscillators are generally not used when accurate frequencies are needed. Delay elements comprising analog circuits can be less sensitive, but are generally not suitable for automated design and layout because the exact layout is important for correct operation, and the deign must be re-optimized for each new IC manufacturing process.
Digitally programmable ring oscillators are one solution to the frequency inaccuracy of digital oscillators. In a digitally programmable ring oscillator, by digitally increasing or decreasing the number of delay elements in the ring, the oscillation frequency can be changed. Decreases in the number of delay elements are always achieved by bypassing some delay elements in one way or another, e.g., a programmable ring oscillator disclosed in U.S. Pat. No. 4,517,532 issued to Neidorff in May 1985. In this oscillator, the resolution of frequency changes is limited by the delay of each delay element used because an even number of inverters must always be added or subtracted from the ring to maintain oscillation. Also, each time the number of inverters in the ring is changed, a transient pulse or “glitch” can be generated at the output.
In a paper entitled, “Integrated Pin Electronics for VLSI Functional Testers” (Gasbarrow & Horowitz, April 1989, IEEE Journal of Solid-State Circuits), the authors show a circuit technique, as shown in circuit
20
of
FIG. 2
, to create a delay line with delay increments less than that of one logic gate. The circuit
20
is used to delay the rising edges of a series of pulses. The designers exploit “the difference in path delay through pairs of carefully sized inverters.” The circuit
20
uses a conventional tapped delay line
24
and multiplexer
23
for the larger delay steps, and parallel inverters
21
and
22
, and
25
-
27
for the smaller delay steps. The transistor sizes of the inverts
21
-
22
,
25
-
27
are shown next to each inverter in FIG.
2
.
Certain characteristics of the design by Gasbarrow & Horowitz can be improved. The authors do not explain how to construct their circuit using only logic gates of a single size. Also, the load capacitance presented by one or two logic gate inputs in present IC technologies is usually too small to cause a significant delay change when the drive of a gate is doubled. Their design, as described, is not suitable for automated design.
U.S. Pat. No. 5,013,944 issued to Fischer et al in May 1991 describes a “Programmable Delay Line Utilizing Measured Actual Delays to Provide a Highly Accurate Delay”. The delay line is schematically depicted in the circuit
30
of FIG.
3
. The delay of a series of delay stages
35
,
36
,
41
is measured by connecting them in a ring oscillator and the delay paths (e.g., path
33
) are selectively bypassed with alternate delay paths (e.g., path
34
) as needed until the oscillation frequency, and hence delay, is sufficiently close to a reference frequency. The difference in delay of each pair of paths (e.g., path
33
and path
34
) is designed to be an approximate value, specifically, the delay of one or more non-inverting logic gates. The ratio of the delay difference of each pair (e.g.,
35
) to the next pair (e.g.,
36
) in the delay line is approximately a factor of two, thus achieving a binary-weighted programmable delay line
30
. For smaller delay increments, one delay path
42
contains a first logic gate
37
, and the other path
43
in the pair contains a second logic gate
38
that has additional logic gates
39
connected in parallel at its output, to increase its delay relative to the first logic gate
37
by less than one logic gate's delay.
Certain characteristics of the design by Fischer et al can cause problems. When the capacitive wire load on the gates in each of two paths is not well matched, the delay through the path
33
with fewer logic gates can inadvertently become longer than the path
34
with more logic gates in series. This prevents a binary search algorithm from working correctly. Also, because the two paths
42
and
43
are connected to different inputs of logic gate
40
, the two inputs can have different switching point voltages which can cause the delay of the shorter path
42
to appear longer than the intended longer path
43
. This effect is exacerbated when additional load capacitance is added to the output of a logic gate. These various effects make the design approach unsuitable for automatic layout. Lastly, for the larger delay changes, glitches can be introduced when switch settings are changed.
If accuracy is to be maintained while a ring oscillator's output is clocking other circuitry, the frequency may need to be changed when it varies significantly from its intended value due to changes in the supply voltage or temperature. Changes in the frequency of a programmable ring oscillator need to be ‘glitcheless’ in such circumstances, otherwise a pulse or ‘glitch’ can be generated which is shorter than the minimum that the clocked circuitry can tolerate, causing incorrect operation. U.S. Pat. No. 5,471,176 issued to Henson et al in November 1995 describes a Glitchless Frequency-Adjustable Ring Oscillator, an embodiment of which is schematically shown in the circuit
50
of FIG.
4
. The circuit
50
seeks to avoid introducing glitches in the output signal
55
when delay stages of a tapped delay line
53
are bypassed by synchronizing the

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