Programmable clock manager for a programmable logic device that

Details Programmable clock manager for a programmable logic device that Programmable clock manager for a programmable logic device that

1997-10-15

2000-03-28

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 37, 326 38, G06F 738

Patent

active

060436778

ABSTRACT:
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.

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