Programmable clock manager for a programmable logic device that

Details Programmable clock manager for a programmable logic device that Programmable clock manager for a programmable logic device that

1997-10-15

2000-05-09

Nelms, David

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, G06F 738

Patent

active

060609028

ABSTRACT:
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.

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