Programmable clock delay

Details Programmable clock delay Programmable clock delay

1999-12-22

2001-08-14

Lam, Tuan T. (Department: 2816)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S276000, C327S270000

Reexamination Certificate

active

06275068

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits, and in particular to a circuit and methodology that allows for the dynamic modification of skew between clocks within a integrated circuit using software.
BACKGROUND OF THE INVENTION
In designing complex systems like today's integrated circuits, where multiple clocks are used, the skew between clocks is often a crucial issue. This is particularly important when the integrated circuit has already been fabricated and it then becomes important to change the delay or skew between clocks. High frequency clock signals can be routed throughout an integrated circuit to multiple blocks of devices such as a hardware accelerators, DSP processors, and random access memories. It is desirable to have clock signals arrive at all hardware blocks at precisely controlled times, which may not be simultaneous. If the correct skew between the competing clocks is not properly set during the design of the integrated circuit, there would be a possibility for race conditions in the circuit and thus system failure. Once the integrated circuit is fabricated skew between clocks is hard tuned i.e. the relationship between the various clocks and the system can not be changed without a mask change which may be very costly and time consuming.
To design clock circuitry and properly set clock skew within an integrated circuit most designers typically use simulation tools. The problem is that simulation tools do not necessarily match the post fabrication characteristics of the integrated circuit. Discrepancies between the simulation models and the physical chip leaves the system susceptible to variations in delays and circuit timing that may not be accounted for. One of the most prevalent variations of this type is clock skew. Designers try to accommodate for clock skew variations in their designs by placing known delays in the circuit or placing clock uncertainties in the design constraints. These techniques usually yields only marginal results.
Another method of solving variations in clock skew is to use more realistic simulation delay models. These models may be developed by extracting the post layout and fabrication parasitic values in order to modify the models. This technique still requires the integrated circuit to be re-simulated with the new models. The integrated circuit must then go back through the fabrication and testing process. Using this technique has the problem of requiring extensive time to re-simulate and complete a second fabrication of the integrated circuit, which may not be possible due to the ever increasing time to market pressure. Even in scenarios where post layout RC parasitic values are taken into account, there would be no guarantee that the fabricated integrated circuit will behave as it was predicted because the models, due to their simplicity, do not necessarily follow the physical design parameters.
SUMMARY OF THE INVENTION
In an integrated circuit, a method of programmably controlling the delay between a second clock signal with respect to a first clock signal after fabricating the integrated circuit. Prior to fabrication, a programmable delay group is formed and will be included in the integrated circuit. The programmable delay group includes a plurality of parallel coupled sets of delay stages with each set having at least one delay stage, serially coupling the delay stages for the sets having more than one delay stage.
After fabrication of the integrated circuit and in operation, the first clock signal is applied to one end of each of the sets of delay stages. The enable signals are generated and applied to the programmable delay group in order to enable one of the sets of delay stages. The enabled set will delay the first clock signal and produce the second clock signal at the other end of the enabled set and hereby controlling the delay of the second clock signal.
In another embodiment, a programmable clock delay system having first and second clock input signals generates first and second clock output signals, skewed with respect to the first and second clock input signals, respectively. This system has a first programmable delay group that includes a plurality of parallel coupled sets of delay stages coupled, all at one end, to the first clock input. Each set of delay stages has at least one delay stage. For the sets having more than one delay stage, each delay stage is serially coupled to the next. The other end of each set is coupled together to produce a first clock output signal for the first programmable delay group.
A second programmable delay group includes a plurality of parallel coupled sets of delay stages coupled, all at one end, to receive the second clock input. Each set of delay stages has at least one delay stage. For the sets having more than one delay stage, each delay stage is serially coupled to the next. The other end of each set is coupled together to produce a second clock output signal for the second programmable delay group.
A first control circuit provides enable signals to a delay stage in each set of the first programmable delay group. The enable signals selectively enable one of the sets of delay stages, which when enabled provides a delay path to delay the first clock input and transmit the first clock output signal. A second control circuit provides enable signals to a delay stage in each set of the second programmable delay group. This selectively enables one of the sets to delay the second clock and transmit the second clock output signal.
A circuit provides programmable control signals to the first and second control circuits to provide first and second clock output signals skewed with respect to the first and second clock input signals, respectively.


REFERENCES:
patent: 5126691 (1992-06-01), Mijuskovic et al.
patent: 5268656 (1993-12-01), Muscavage
patent: 5438300 (1995-08-01), Saban et al.
patent: 5828870 (1998-10-01), Gunadisastra
patent: 5838179 (1998-11-01), Schmidt
patent: 5841296 (1998-11-01), Churcher et al.
patent: 5881271 (1999-03-01), Williams
patent: 5923611 (1999-07-01), Ryan
patent: 5926837 (1999-07-01), Watanabe et al.
patent: 6046620 (2000-04-01), Relph
patent: 6130567 (2000-10-01), Kobayashi
patent: 6150863 (2000-11-01), Conn et al.
patent: 64-1322-a (1989-01-01), None

Affiliated with

Also associated with

Rating

Programmable clock delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable clock delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable clock delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2490803