Programmable clock control architecture for at-speed testing

Details Programmable clock control architecture for at-speed testing Programmable clock control architecture for at-speed testing

2011-01-04

2011-01-04

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S500000, C713S600000

Reexamination Certificate

active

07865759

ABSTRACT:
According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The N-stage programmable clock control architecture further includes means for programming the N flip-flops such that the N-stage programmable clock control architecture outputs N programmed at-speed clock pulses. For example, when N is equal to 3, three programmed clock pulses can be outputted by the N-stage programmable clock control architecture, with a total of eight different patterns of programmed clock pulses. The N-stage programmable clock control architecture can thus adequately test, for example, combinational logic requiring greater than two consecutive clock pulses for complete at-speed testing. In one embodiment, scan-shift registers can be utilized to program the N flip-flops. In another embodiment, a look-up table can be used to program the N flip-flops.

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Iyengar, et al.,At-Speed Structural Test for High-Performance ASICs, International Test Conference, pp. 1-10 (2006 IEEE).

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