Programmable circuit structures with reduced susceptibility...

Details Programmable circuit structures with reduced susceptibility... Programmable circuit structures with reduced susceptibility...

2002-06-13

2003-12-30

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230020, C326S112000, C326S113000

Reexamination Certificate

active

06671202

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to circuit structures susceptible to single event upsets, such as those in programmable logic devices (PLDs). More particularly, the invention relates to programmable circuit structures on which single event upsets have a reduced impact.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal wires). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). A PIP can be, for example, a pass gate. When the pass gate is turned on, the two nodes on either side of the pass gate are electrically connected. When the pass gate is turned off, the two nodes are isolated from each other. Thus, by controlling the values on the gate terminals of the pass gates, circuit connections can easily be made and altered.
The logic blocks and PIPs in a PLD are typically programmed (configured) by loading configuration data into thousands of configuration memory cells. In Field Programmable Gate Arrays (FPGAs), for example, each configuration memory cell is implemented as a static RAM cell. These static RAM cells are used, for example, to control the gate terminals of pass gates between pairs of interconnect lines.
When subjected to unusual conditions such as cosmic rays or bombardment by neutrons or alpha particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. Sometimes these “single event upsets” have no effect on the functionality of the chip, for example, when the static RAM cell controls a pass gate between two unused interconnect lines. At other times, a single event upset can change the functionality of a configured PLD such that the circuit no longer functions properly.
FIG. 1
shows an exemplary programmable circuit that is subject to the effects of single event upsets. The circuit of
FIG. 1
is a programmable multiplexer circuit that includes several pass gates. This type of circuit is commonly included in FPGA interconnect structures, for example. The circuit selects one of several different input signals and passes the selected signal to an output node.
The circuit of
FIG. 1
includes 16 input terminals IN
0
-IN
15
and 20 pass gates
100
-
115
,
120
-
123
that selectively pass one of signals IN
0
-IN
15
, respectively, to an internal node INT. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The signal on internal node INT is buffered by buffer BUF to provide output signal OUT.
Buffer BUF, for example, can include two inverters
131
,
132
coupled in series, and a pull up (e.g., a P-channel transistor
133
to power high VDD) on internal node INT and driven by the node between the two inverters. However, buffer BUF can be implemented in many different ways.
Each pass gate
100
-
115
has a gate terminal driven by one of memory cells M
4
-M
7
. Each pass gate
120
-
123
has a gate terminal driven by one of memory cells M
0
-M
3
, respectively. Each memory cell can include two cross-coupled inverters An, Bn, for example. Memory cells M
0
-M
7
can be implemented in many different ways. However, aside from shared configuration logic (i.e., logic for loading and sometimes reading back the contents of the memory cell), memory cells M
0
-M
7
operate independently of each other.
The programmable multiplexer circuit of
FIG. 1
operates as shown in Table 1. At most, one of memory cells M
4
-M
7
and one of memory cells M
0
-M
3
can be configured with a high value at any given time. Other configurations are not supported by the circuit. As can be seen from Table 1 and
FIG. 1
, the one of memory cells M
4
-M
7
with a high value selects four input signals to be passed to internal nodes INT
0
-INT
3
. The one of memory cells M
0
-M
3
with a high value then selects one of the signals on nodes INT
0
-INT
3
to be passed to node INT, and hence to output node OUT. If none of memory cells M
0
-M
7
is configured with a high value, output signal OUT is held at its initial high value by pullup
133
.
TABLE 1
M7
M6
M5
M4
M3
M2
M1
M0
OUT
0
0
0
0
0
0
0
0
High
0
0
0
1
0
0
0
1
IN0
0
0
1
0
0
0
0
1
IN1
0
1
0
0
0
0
0
1
IN2
1
0
0
0
0
0
0
1
IN3
0
0
0
1
0
0
1
0
IN4
0
0
1
0
0
0
1
0
IN5
0
1
0
0
0
0
1
0
IN6
1
0
0
0
0
0
1
0
IN7
0
0
0
1
0
1
0
0
IN8
0
0
1
0
0
1
0
0
IN9
0
1
0
0
0
1
0
0
IN10
1
0
0
0
0
1
0
0
IN11
0
0
0
1
1
0
0
0
IN12
0
0
1
0
1
0
0
0
IN13
0
1
0
0
1
0
0
0
IN14
1
0
0
0
1
0
0
0
IN15
In the multiplexer circuit of
FIG. 1
, the upset of any single memory cell (i.e., any single event upset affecting any of memory cells M
0
-M
7
) causes a failure in the circuit. For example, assume that memory cells M
4
and M
0
store high values, while memory cells M
1
-M
3
, M
5
-M
7
store low values. The selected input signal is IN
0
. Pass gates
112
,
108
,
104
,
100
,
120
are enabled, and all other illustrated pass gates are disabled. If the value in memory cell M
7
is upset (i.e., changes to a high value), pass gate
103
is enabled and there is a “short” (an inadvertent coupling) between input terminals IN
0
and IN
3
. Similarly, if the value in memory cell M
2
is upset, pass gate
122
is enabled and there is a short between nodes IN
0
and IN
8
, and so forth. If the value in either of memory cells M
4
and M
0
is upset (i.e., changes to a low value), the path from input terminal IN
0
to output terminal OUT is broken, and output signal OUT is no longer actively driven by node IN
0
.
Thus, the multiplexer circuit of
FIG. 1
is one example of a programmable circuit that is susceptible to single event upsets.
In general, larger circuits that include more memory cells are more susceptible to single event upsets than smaller circuits with fewer memory cells. For example, a configurable logic block (CLB) in an FPGA can include several hundred memory cells. A single event upset in any one of these memory cells can cause an error in a user circuit implemented in the CLB. PLDs and logic blocks are growing progressively larger and more complicated over time, and the number of memory cells included in PLDs is increasing as a result.
Further, as operating voltages diminish, static RAM cells become more susceptible to changes in state caused by single event upsets. To reduce manufacturing costs, PLD manufacturers are aggressively reducing device sizes in their PLDS. These smaller devices often operate at lower voltages.
Therefore, the effects of single event upsets are becoming more important over time. Hence, it is desirable to provide PLD circuits with reduced susceptibility to single event upsets.
SUMMARY OF THE INVENTION
The invention provides circuit structures for programmable logic devices (PLDS) that have reduced susceptibility to single event upsets. A circuit structure according to the invention includes a programmable circuit controlled by memory cells. The programmable circuit is designed such that at most one of the memory cells in a group of the memory cells has an enable value at any given time. According to the invention, the memory cells are coupled together such that if any one memory cell in the group is at an enable value (e.g., high), then all other memory cells in the same group are forced to a disable value (e.g., low).
If a single event upset occurs at any of the memory cells that are configured to provide disable values (“disabling memory cells”), the value in the memory cell does not change, because the memory cell is being held disabling by the one enabling

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