Programmable chip bus arbitration logic

Details Programmable chip bus arbitration logic Programmable chip bus arbitration logic

2005-09-21

2008-07-01

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S116000, C710S241000, C710S244000, C710S265000

Reexamination Certificate

active

07395360

ABSTRACT:
Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.

REFERENCES:
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patent: 6516369 (2003-02-01), Bredin
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patent: 2004/0258086 (2004-12-01), Kurupati
John Rynearson, “VMEbus Arbitration” VITA Journal, www.vita.com, Mar. 1997, 3 pages.
Huajin et al., “Design Fast Round Robin Scheduler in FPGA” IEEE, 2002, pp. 1257-1261.
Paul Metzgen, “A high performance 32-bit ALU for programmable logic” Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, Feb. 22-24, 2004, Monterey, California, USA.

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