Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-02-26
1999-06-15
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711167, 711145, 711144, G06F 1214
Patent
active
059132248
ABSTRACT:
A computer system is disclosed which provides for execution of real-time code from cache memory. A cache management unit provides the real-time code to the cache memory from system memory upon a initiation of a read operation by a processor. Once in cache memory, the processor executes the real-time code from cache memory instead of system memory. The cache management unit detects read hits to cache each time the processor requests an instruction of code that is stored in the cache memory. Lock bits associated with each line of cache lock the contents of the line preventing the line from being overwritten under normal cache operation in which the least most recently used cached data is replaced by presently accessed data. Alternatively, one of a plurality of cache data ways may be dedicated to storing real-time code. Real-time code stored in the dedicated data way is not replaceable and thus is locked.
REFERENCES:
patent: 5353425 (1994-10-01), Malamy et al.
patent: 5487162 (1996-01-01), Tanaka et al.
patent: 5638537 (1997-06-01), Yamada et al.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Langjahr David
Swann Tod R.
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