Programmable bus hold circuit and method of using the same

Details Programmable bus hold circuit and method of using the same Programmable bus hold circuit and method of using the same

1998-09-16

2001-02-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S056000, C326S083000

Reexamination Certificate

active

06191607

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of computer input/output devices, and more specifically, to circuits that reduce input/output bus contention as may be used in such devices.
BACKGROUND
Conventional input/output (“I/O”) devices commonly used in computer systems are often required to quickly drive I/O buses that are connected to I/O pins in order to meet various timing specifications. To meet these requirements, I/O devices are typically equipped with output drivers that have high signal switching strengths. When the output driver is turned off there is a potential problem on the bus. A user may pull the bus either high or low with external circuitry, but this may cause excess noise due to many outputs switching simultaneously. Accordingly, a conventional solution of preventing bus contention is to add a bus hold circuit (e.g., configured as a weak latch).
Although using bus hold circuits reduces the bus noise level, bus hold circuits are not always needed or desirable. For example, if an application requires that multiple I/O pins be tied together, a number of individual bus hold circuits associated with these pins may consume a large amount of operating current. Consequently, a voltage level held by the multiple bus hold circuits may tend to be more difficult to override. Further, some users may wish to purchase I/O devices that are not constructed with bus hold circuits because of the expected cost savings which may result. Unfortunately, it would be cost prohibitive for a manufacturer to produce two identical devices with one version having bus hold circuits and another without such circuits. Thus, a solution is needed.
SUMMARY OF THE INVENTION
A programmable bus hold circuit which may find application in programmable logic devices, memories and other I/O devices may include a first element for receiving a voltage from an I/O pad and programmable circuitry coupled to the first element for controlling whether the voltage at the pad is to be held its current logic level. The first element may be a logic gate (such as a NOR gate) the programmable circuit may include a tristatable buffer (e.g., under the control of a memory cell or other programmable bit capable of enabling or disabling the programmable bus hold circuit) or a switch (e.g., a transistor).


REFERENCES:
patent: 5027012 (1991-06-01), Saeki et al.
patent: 5668482 (1997-09-01), Roskell
patent: 5739702 (1998-04-01), Shigehara et al.
patent: 5764075 (1998-06-01), Fukushima
patent: 5894230 (1999-04-01), Voldman

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