Programmable bit ordering for serial port

Details Programmable bit ordering for serial port Programmable bit ordering for serial port

2001-12-19

2003-07-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S090000, C710S107000, C710S109000, C710S110000

Reexamination Certificate

active

06586968

ABSTRACT:

FIELD
The subject matter herein relates to serial ports that receive and transmit information with a most significant bit (MSB) first or a least significant bit (LSB) first. More specifically, the subject matter herein relates to a serial port that can be programmed, or configured, to handle information that is received and transmitted either MSB first or LSB first.
BACKGROUND
A serial port, or bus, for a computerized system transfers information one bit at a time, rather than several bits at a time, as does a parallel port or bus. A byte (eight bits) of information is thus typically transferred at a rate of one bit per clock cycle (i.e. eight clock cycles) of a supplied clock.
A byte is typically defined by a most significant bit (MSB) and a least significant bit (LSB). When transferred through a serial port, the MSB or LSB of the byte must be transferred first, with the remaining bits following in order.
An example in which data is transferred MSB first is illustrated by a timing diagram
100
shown in FIG.
1
. When serial data transfer is enabled (e.g. by an “enable” signal
102
), “data” signals, or bits,
104
are latched on each cycle of a clock signal
106
. In a conventional synchronous serial bus transfer, an initial bit (RAW)
108
of a first byte
110
indicates whether the operation is for reading from or writing to a target, such as a memory space or register (not shown) in the serial port (not shown). Subsequent bits
112
of the first byte supply the address of the target, starting with the MSB (A
6
) and ending with the LSB (A
0
). For a write operation (e.g. R/W=0), a subsequent byte
114
supplies a byte of the data to be written to the target, starting with the MSB (D
7
) and ending with the LSB (D
0
).
An example in which data is transferred LSB first is illustrated by a timing diagram
116
shown in FIG.
2
. In this case, when serial data transfer is enabled (e.g. by an “enable” signal
118
), and after the initial R/W bit
120
is received in a first bit of a first byte
122
in a first cycle of a clock signal
124
, the remaining bits
126
of the first byte
122
supply the address for the target (not shown), starting with the LSB (A
0
) and ending with the MSB (A
6
). For a write operation (R/W=0), a subsequent byte
128
supplies a byte of the data, starting with the LSB (D
0
) and ending with the MSB (D
7
).
Different hardware (e.g. devices, integrated circuits “IC's” or logic), that receive and transmit information in serial, however, do not all transmit the bits in the same order (i.e. MSB first or LSB first). When two or more IC's that do not transmit the bits in the same order are to be used together, one of the IC's must be redesigned to be compatible with the other IC. A redesign is typically costly and time-consuming.
It is with respect to these and other background considerations that the subject matter herein has evolved.
SUMMARY
The subject matter described herein involves a device, integrated circuit (IC) or logic, for use in serial data transfer, that can be configured, or programmed, to handle data in either an MSB first or LSB first operational mode, so it can be used with any other circuitry without having to redesign the IC or the other circuitry, regardless of the order in which the IC and the other circuitry handle the data. A controller, such as, but not necessarily, a type that operates on software or firmware, sends a command to the IC instructing the IC on the mode (i.e. MSB or LSB first) with which to handle the serial data.
In a particular embodiment, the command has a “mirrored” bit pattern, meaning that the bits of the command are the same whether received MSB first or LSB first. The command may further involve a mirrored bit pattern for a reserved address (e.g. for a register) in the IC to which another particular mirrored bit pattern is written to cause the IC to use the desired operational mode.
In another particular embodiment, one of the operational modes (i.e. MSB first or LSB first) is a default, so the command is sent only if the other operational mode is required. In this manner, configuration of the IC is simplified.
In another particular embodiment, a device in which the IC is incorporated has more than one such IC, each connected to some other circuitry. Some of the IC's may have to operate MSB first, and the rest of the IC's may have to operate LSB first, depending on the operational mode of the other circuitry connected to each IC. Thus, the controller sends commands to each such IC separately instructing them on the operational mode that they are to use.
A more complete appreciation of the present disclosure and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.


REFERENCES:
patent: 5341131 (1994-08-01), Hoshino et al.
patent: 5819051 (1998-10-01), Murray et al.
patent: 6122694 (2000-09-01), Horiguchi
patent: 6359951 (2002-03-01), Morriss et al.

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