Programmable bias for a memory array

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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Details

C365S185250, C365S185180, C365S189090, C365S225700

Reexamination Certificate

active

07542360

ABSTRACT:
A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

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patent: 7080267 (2006-07-01), Gary et al.
patent: 2005/0091629 (2005-04-01), Eisenstadt et al.
patent: 1402531 (2006-08-01), None
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James W. Tschanz, James T. Kao, Siva G. Narendra, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan, and Vivek De, “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1396-1402.
Lawrence T. Clark, Michael Morrow, and William Brown, “Reverse-Body Bias and Supply Collapse for Low Effective Standby Power” IEEE Transactions on Very Large Scale Integration Systems, vol. 12, No. 9, Sep. 2004, pp. 947-956.

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