Programmable bias circuit architecture for a digital...

Details Programmable bias circuit architecture for a digital... Programmable bias circuit architecture for a digital...

2008-04-10

2010-11-02

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189070, C365S193000

Reexamination Certificate

active

07826279

ABSTRACT:
Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage.

REFERENCES:
patent: 7109770 (2006-09-01), Bui
patent: 7180352 (2007-02-01), Mooney et al.
patent: 7256652 (2007-08-01), Fang et al.
patent: 2005/0035820 (2005-02-01), Pessl
Jedec Standard, “DDR2 SDRAM Specification”, JESD79-2C (Revision of JESD79-2B) Jedec Solid State Technology Association, May 2006.

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