Programmable asynchronous pipeline arrays

Details Programmable asynchronous pipeline arrays Programmable asynchronous pipeline arrays

2007-01-02

2007-01-02

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C326S046000, C708S490000

Reexamination Certificate

active

10921349

ABSTRACT:
High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the designer needing to be explicitly aware of all pipelining details. The FPGAs include arrays of logic blocks or cells that include function units, conditional units and other elements, each of which is constructed using basic asynchronous pipeline stages, such as a weak condition half buffer and a precharge half buffer.

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