Programmable array interconnect network

Details Programmable array interconnect network Programmable array interconnect network

1995-06-02

1997-05-20

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19177

Patent

active

056315783

ABSTRACT:
A programmable interconnection system for a programmable array includes pluralities of parallel buses for rows and columns of logic cells arranged in the array. Two groups of seven buses are provided for each row or column of logic cells. The buses include conductors connectable to each other, and selectively connectable to, or isolated from, the logic cells. A hierarchy of conductor lengths is disclosed to provide intra-sector and inter-sector bussing. Staggered switching is employed for adjacent sector access.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 5055718 (1991-10-01), Galbraith et al.
patent: 5073729 (1991-12-01), Greene et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5187393 (1993-02-01), El Gamal et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5212652 (1993-05-01), Agrawal et al.
patent: 5218240 (1993-06-01), Camarota et al.
patent: 5231588 (1993-07-01), Agrawal et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5245227 (1993-09-01), Furtek et al.
patent: 5255203 (1993-10-01), Agrawal et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5298805 (1994-03-01), Garverick et al.
patent: 5317209 (1994-05-01), Garverick et al.
patent: 5319254 (1994-06-01), Goetting
patent: 5323069 (1994-06-01), Smith, Jr.
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5338984 (1994-08-01), Sutherland
patent: 5455525 (1995-10-01), Ho et al.
patent: 5469003 (1995-11-01), Kean
F. Furtek, "An FPGA Architecture for Data-Path Applications", IEEE Computer Society Press, Feb. 1993, pp. 374-377.
M. Khellah, et al., "Minimizing Interconnection Delays in Array-based FPGAs", IEEE, 1994, Custom INtegrated Circuits Conference, pp. 181-184.
T. Kean, PCT Patent Application WO 94/10754, "Improved Configurable Cellular Array", May 11, 1994.
Atmel, "Field Programmable Gate Arrays AT6000 Series", 1993, pp. 1-16.
Motorola, "Product Brief, MPA10xx Field Programmable Gate Arrays," dated Sep. 27, 1993.
Payton, M., "The Motorola PFGA," Briefing, 22 pgs., dated Sep. 14, 1993.

Affiliated with

Also associated with

Rating

Programmable array interconnect network does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable array interconnect network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable array interconnect network will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1726518