Programmable array clock/reset resource

Details Programmable array clock/reset resource Programmable array clock/reset resource

1995-06-02

1997-07-29

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 39, 326 98, H03K 19177

Patent

active

056525290

ABSTRACT:
A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

REFERENCES:
patent: 5309046 (1994-05-01), Steele
patent: 5457409 (1995-10-01), Agrawal et al.
patent: 5506517 (1996-04-01), Tsui et al.

Affiliated with

Also associated with

Rating

Programmable array clock/reset resource does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable array clock/reset resource, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable array clock/reset resource will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-636180