Programmable array and method for routing power busses therein

Electronic digital logic circuitry – Multifunctional or programmable – Array

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326 47, 326101, H03K 19177

Patent

active

057572089

ABSTRACT:
A programmable array (10) includes an array (11) of transistor cells, output cells (26, 28, 32, 34), and two internal power busses (17, 18) which are coupled to the array (11) of transistor cells. The programmable array also includes eight output power busses (35, 36, 37, 38, 41, 42, 43, 44) coupled to the output cells (26, 28, 32, 34). The two internal power busses (17, 18) are coupled to two corresponding output power busses (35, 36) via two coupling switches (55, 56). Further, the output power busses (35, 36, 37, 41, 42, 43, 44) are coupled to each other via eight switches (45, 46, 47, 48, 51, 52, 53, 54). Different power bus routings of the programmable array (10) are realized by controlling the two coupling switches (55, 56) and the eight switches (45, 46, 47, 48, 51, 52, 53, 54).

REFERENCES:
patent: 4511914 (1985-04-01), Remedi et al.
patent: 4661815 (1987-04-01), Takayama et al.
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 5079612 (1992-01-01), Takamoto et al.

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