Electrical computers and digital processing systems: support – Computer power control – Power sequencing
Reexamination Certificate
1998-10-09
2001-04-03
Myers, Paul R. (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power sequencing
C713S323000, C713S324000
Reexamination Certificate
active
06212645
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to computer systems, and more particularly relates to managing power sequences to disable and enable circuits.
BACKGROUND OF THE INVENTION
With the advances of semiconductor and computer technology, computer systems are becoming faster and at the same time smaller in size. Desk-top and even lap-top computer systems now possess processing speeds of main-frame computers that used to fill up a small room. Even hand-held computer systems such as personal digital assistants (PDA), which are becoming more popular, are getting more powerful. As computer systems become more miniaturized and inexpensive, more demands are constantly being required of them as well. One such demand is speed or performance.
At the same time, as computer systems become more powerful and more miniaturized, power-conservation also presents a difficult challenge to overcome. Because of their small size, hand-held computer systems are powered by battery which have limited operating duration. Since more power is required for faster and more powerful processors, innovative solutions are required to conserve power and thereby extend the battery operating duration.
Within each computer system are many integrated circuits designed to perform different functions such as a memory controller, a hard disk controller, a graphics/video controller, a communications controller, and other peripheral controllers. As is well-known, each of these integrated circuits is supplied a clock signal to be used as a timing reference in synchronizing the operation of the integrated circuit. In general, power consumption increases as a result of the integrated circuit being clocked faster.
Periodically, an integrated circuit is not needed and is idle insofar as system functionality is concerned. At other times, while a sub-circuit (e.g., combination logic and data path) that performs data processing and transferring in the integrated circuit is still running, other sub-circuits in the integrated circuit are idle. Because these sub-circuits continue to receive a clock signal, their respective internal sub-circuits continue to be exercised and consume significant power, even while they remain idle. Accordingly, to conserve power, the clock signal to idle sub-circuits is disabled. The clock signal to these sub-circuits are then enabled as necessary. Powering up (enabling) and powering down (disabling) selected sub-circuits in an integrated sub-circuit may occur in a required sequence. Such power sequencing is required because some sub-circuits are dependent on other sub-circuits. For example, a sub-circuit needs to be powered up before another sub-circuit can be powered up. Power sequencing is also required when a sub-circuit needs a sequence of input signals to turn on or off as in the case of some synchronous dynamic Random Access Memory (RAM) or a Liquid Crystal Display (LCD) flat panel monitor. Such power sequence is important because if the sequence is not done properly then some circuitry blocks will not be enabled properly.
Power Management Units (PMUS) are typically used to provide the desired power sequencing. Conventional PMUs, however, can only power up or power down selected sub-circuits in one sequence. In other words, conventional PMUs do not have the capability to power up selected sub-circuits and power down other selected sub-circuits in the same sequence. This inflexibility greatly restricts the power sequencing applications of conventional PMUs. Moreover, the power sequences in conventional PMUs are normally predefined which further restrict the applications of conventional PMUs.
Thus, a need exists for a PMU that allows for power up sequencing as well as power down sequencing to occur in one sequence and for selectively powering up and powering down circuits in a power sequence.
SUMMARY OF THE INVENTION
The present invention meets the above need with a programmable and flexible Power Management Unit (PMU). The PMU comprises: a counter circuit, a state machine, a decoder, and a plurality of enable circuits. The counter circuit receives as inputs interval control signals. The counter circuit monitors power sequencing intervals in response to the interval control signals. The counter circuit generates signals indicating whether the power sequencing intervals have expired. The state machine receives as inputs the power sequencing interval status signals and state control signals. In response to the state control signals, the state machine selects a main power state for the PMU, wherein each main power state has N sub-states organized in a sequence. In response to the power sequencing interval status signals, the state machine selects a sub state for the PMU. The state machine generates signals indicating the main power state and sub-state that the state machine is currently engaged.
The decoder circuit receives as inputs the signals from the state machine. In response to the signals from the state machine, the decoder circuit monitors status of the main power state and sub-state that the state machine is currently engaged in and generates status signals to indicate the status of the main power state and sub-state. The plurality of enable circuits receives as inputs the signals from the state machine, the status signals from the decoder circuit, and select signals. The plurality of enable circuits generates signals to enable selected circuits.
All the features and advantages of the present invention will become apparent from the following detailed description of its preferred embodiment whose description should be taken in conjunction with the accompanying drawings.
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Mediaq Inc.
Myers Paul R.
Nguyen & Associates
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