Programmable and electrically configurable latch timing circuit

Details Programmable and electrically configurable latch timing circuit Programmable and electrically configurable latch timing circuit

1999-12-29

2002-10-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S194000, C365S201000, C365S233100

Reexamination Certificate

active

06462998

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to latch timing control when sensing differential signals in an integrated circuit, and particularly to sensing differential signals within or associated with a semiconductor memory array such as a dynamic random-access memory array.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
Common to many integrated circuits incorporating dynamic memory arrays are dynamic latching sense amplifiers. These are used as bit line sense amplifiers to sense the small differential voltage on the complementary pairs of bit lines, and also as data line amplifiers to sense a small differential voltage between other complementary nodes, such as data lines, data buses, global data buses, and other pairs of circuit nodes. Such latching sense amplifiers are also advantageously employed on other kinds of integrated circuits, such as, for example, those incorporating static memory arrays, non-volatile memory arrays, long capacitively-loaded data buses, and others.
Such latching sense amplifiers are particularly efficient in terms of power and layout area. If the sense enable timing signal (i.e., latch enable signal) for the sense amplifier is provided just after a sufficient differential signal is provided into the sense amplifier, the sensing and latching of the sense amplifier is typically much faster than a linear sense amplifier would be able to provide an output signal with a similar voltage gain. However, if the latching sense amplifier is “latched” later than the optimal time, the output signal will of course be generated later than it otherwise could have been generated, and performance will suffer. Worse, if the latching sense amplifier is enabled to sense (i.e., “is latched”) before sufficient differential signal is developed and provided into the latching sense amplifier, then the latching sense amplifier may very well latch “incorrectly” and, while the latching sense amplifier may be fast, the data latched is erroneous and this erroneous data remains latched for as long as the latch enable signal remains active. Unlike a linear amplifier which eventually will amplify an increasing input differential signal and develop a correct output signal, a latching sense amplifier will not respond to the increasing input differential signal if latched prematurely and its output signal driven incorrectly.
Consequently, latching sense amplifiers are desirable for their efficiency of power and layout area, and if timed appropriately, their speed. Given the usually catastrophic results of latching such a latching sense amplifier too early, integrated circuits that incorporate latching sense amplifiers are usually designed to provide substantial timing margins. Such timing margins, to the extent that they exceed that necessary for reliable operation of the integrated circuit, degrade the performance otherwise achievable from a given design and/or technology.
SUMMARY OF THE INVENTION
Such latch timing margins may be reduced by using a latch timing circuit for controlling the timing of a latch enable signal which is both programmable and electrically configurable. Using the configurable capability, an integrated circuit may be tested while varying the latch enable timing to determine the most aggressive timing for which that particular integrated circuit functions without error. The latch timing circuit is also programmable so that this timing, or another timing, such as a somewhat less aggressive timing, may be programmed to thereafter be the timing normally generated by the latch timing circuit. For certain embodiments the latch timing circuit, after programming its timing, may again be temporarily configured to a more or less aggressive timing relative to the programmed timing, so that adequate operating margins may be ensured, or so that additional characterization testing may be performed. Each particular integrated circuit may be tested to more optimally set the latch timing required by the individual integrated circuit. Integrated circuits whose transistors and other internal components are capable of shorter latch delays, such as those whose threshold voltages are well matched in the latch circuits, or those having a particularly fast data path, may be shipped as higher performance circuits, while those integrated circuits whose transistors and other internal components require longer latch delays may nonetheless be shipped as slower performing, yet fully functioning circuits.
In one embodiment of the present invention suitable for use in an integrated circuit including a latch circuit for sensing and latching, at a particular time when enabled by a latch enable signal, a differential signal that increases in magnitude over a period of time, a latch timing circuit includes an input terminal for receiving an input timing signal, and an output terminal for conveying an output timing signal for controlling the timing of the latch enable signal. A delay circuit is coupled between the input terminal and the output terminal, the delay circuit providing a plurality of different delay times through the delay circuit. The latch timing circuit further includes at least one configuration input terminal for receiving an electrical configuration signal for selecting one of the plurality of different delay times through the delay circuit, such that the latch enable signal is electrically configurable to occur, after receiving the input timing signal, at one of a plurality of various times corresponding to various magnitudes of the differential signal. The latch timing circuit further includes at least one programmable device responsive to a programming stimulus for selecting one of the plurality of different delay times through the delay circuit, such that the latch enable signal is programmable to occur, after receiving the input timing signal, at one of the plurality of various times corresponding to various magnitudes of the differential signal.
In another embodiment of the present invention suitable for use in an integrated circuit including a latch circuit for sensing and latching, at a particular time when enabled by a latch enable signal, a differential signal that increases in magnitude over a period of time, a latch timing circuit includes a first configurable delay circuit having an input terminal for receiving an input timing signal and having an output terminal for conveying an output timing signal for controlling the timing of the latch enable signal. The first configurable delay circuit is responsive to a plurality of timing settings, various individual timing settings of said plurality providing for different delays through the first configurable delay circuit such that the latch enable signal is selectable to occur, after receiving the input timing signal, at one of a plurality of various times corresponding to various magnitudes of the differential signal. The latch timing circuit further includes a first timing setting control circuit for generating and communicating a selected one of the plura

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