Programmable address decoder for programmable logic device

Details Programmable address decoder for programmable logic device Programmable address decoder for programmable logic device

1996-08-07

1998-10-13

Tokar, Michael J.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, H03K 19173, H03K 738

Patent

active

058217720

ABSTRACT:
For an FPGA having a configuration memory arranged in rows and columns, a programmable address decoder with a counter selects the order in which columns of memory cells will be programmed and selects which columns of memory cells are programmed. The decoder structure addresses a particular column only when an address provided by the counter matches an address in the memory cells of the decoder for that column. Bitstreams intended for older devices can be successfully loaded into newer devices. Bitstreams developed for future devices with additional features can be loaded into devices with fewer features, and the additional features are not used. The counter can be set to count not in sequential order so that if extra columns are provided, a defective column of the FPGA controlled by a corresponding column of configuration memory cells can be bypassed.

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