Program thread syncronization for instruction cachelines

Details Program thread syncronization for instruction cachelines Program thread syncronization for instruction cachelines

2005-11-10

2009-06-30

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S151000, C711S154000, C718S101000, C718S108000

Reexamination Certificate

active

07555607

ABSTRACT:
In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by rendering the determined instruction cache line unavailable. Execution of the threads resumes by rendering the determined instruction cache lines available.

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