Program thread syncronization

Details Program thread syncronization Program thread syncronization

2011-07-19

2011-07-19

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S151000, C711S154000, C718S101000, C718S108000

Reexamination Certificate

active

07984242

ABSTRACT:
A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.

REFERENCES:
patent: 5611070 (1997-03-01), Heidleberger et al.
patent: 5923855 (1999-07-01), Yamazaki
patent: 6052761 (2000-04-01), Hornung et al.
patent: 6216174 (2001-04-01), Scott et al.
patent: 6263406 (2001-07-01), Uwano et al.
patent: 7512950 (2009-03-01), Marejka
patent: 7587584 (2009-09-01), Enright et al.
patent: 2004/0187118 (2004-09-01), Blainey et al.
patent: 2005/0050374 (2005-03-01), Nakamura et al.
patent: 2005/0283780 (2005-12-01), Karp et al.
patent: 2006/0143361 (2006-06-01), Kottapalli et al.
patent: 2007/0113233 (2007-05-01), Collard et al.
patent: 9926148 (1999-05-01), None
Sampson et al., “Fast Synchronization fro Chip Multiprocessors,” ACM SIGARCH Computer Architecture News, vol. 33, No. 4, pp. 64-69, Sep. 2005.
G. Almasl et al., Design and Implementation of Message-Passing Services for the Blue Gene/L Supercomputer, IBM Journal of Research and Development, Mar. 2005, 49(2/3):393-406, International Business Machines Corp., Annonk, NY.
Carl J. Beckman et al., Fast Barrier Synchronization Hardware, Proceedings of the 1990 conference on Supercomputing, 1990, pp. 180-189, IEEE Computer Society Press, Los Alamitos, CA.
John M. Mellor-Crummey et al., Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors, ACM Transactions on Computer Systems, 1991,9(1):21-56, ACM Press, New York, NY.
Zhang et al: “Busy-Wait Barrier Sync. Using Distrubted Counters” w/Local Sensors, WOMAT 03, (online) Jun. 23, 2003 www.springerlink.com/contenUat05ttvlfngbqgpp/fulitext.pdf>.
Masahiko Iwani et al; “Tagged Communication ansd Sync. Memory for Multiprocessor-on-a-chip”, Sys & comp in JP, Wiley, Hoboken, NJ, US vol. 32, on Apr. 4, 2001, pp. 1-13.
Lee J et al: Synchronization with Multiproccessor caches. Proceedings of the Annual International Symposium on Computer Architecture, Seattle, May 18-31, 1990 pp. 33.
Beckmann C J et al: Fast Barrier Sync. Hardware. Proceedings of the Supercomputing Conf., NY, Nov. 12-16 1990, Washington, IEEE camp. SOC, PRess, US vol. Conf. 3 pp. 180-189.
J Sampson et al: Fast Synch. for Chip Multiporcessor. AMC Sigarch Special Issue Das; CMO'05 (online) Nov. 13, 2005 pp. 64-69 www.cse.ucsd.edu/{rakumar/dasCMP05/papter07.pdf.

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