Data processing: measuring – calibrating – or testing – Testing system – Including program set up
Reexamination Certificate
1999-08-31
2002-06-11
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Including program set up
C702S117000, C714S741000, C714S724000, C714S730000, C365S201000
Reexamination Certificate
active
06405150
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention, as recited by the claims, covers a program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length. In the prior art, a related electronic system for testing chips is disclosed in U.S. Pat. No. 5,390,129. This prior art system is assigned to Unisys Corporation, who also is the assignee of the present invention.
A simplified block diagram of the prior art chip testing system is shown in
FIG. 2
of patent '129. That system includes a computer
50
which is coupled via a time-shared bus
52
to a plurality of driver boards
100
; and each driver board
100
is coupled to a respective burn-in board
500
which holds several integrated circuit chips that are to be tested.
In operation, the computer
50
sequentially sends each driver board
100
a separate set of test data patterns that are used to test the chips. These test data patterns are stored on each driver board in a large SRAM which is shown in
FIG. 3
by reference numeral
107
and is shown in greater detail in
FIG. 9
by reference numeral
145
. Which particular driver board receives and stores the test data patterns at any one time is determined by an address circuit
100
A that is on the driver board, as is shown in the
FIG. 2
block diagram.
After the test data patterns are stored in the SRAM
145
on all of the driver boards
100
, then the chips on all of the burn-in boards
500
can be tested in parallel. To do that, the test patterns are concurrently read from all of the SRAMs and sent through respective output driver modules
164
, as shown in
FIG. 14
, to the chips on all of the burn-in boards
500
.
One particular feature of the chip testing system in patent '129 is that each burn-in board includes an ID code which identifies the types of chips that are to be tested on the board. That ID code is sensed by the driver board
100
and sent to the computer
50
; and in response, the test data patterns which the computer
50
sends to the driver board are tailored to the ID code that is sensed.
However, the chip testing system in patent '129 also has some major limitations which are imposed by the
FIG. 2
architecture. For example, the computer
50
is the sole source of the test data patterns for all of the driver boards
100
. Consequently, the speed of operation of the chip testing system is limited because the computer
50
can only send the test data patterns to a single driver board at a time over the bus
52
.
Another limitation of the chip testing system in patent 3 129 is that each driver board
100
always tests all of the chips on a burn-in board
500
concurrently. However, each burn-in board inherently has a limit on the total amount of power which the chips on the board can dissipate. Thus, in order to keep the total power dissipation on each burn-in board
500
below a certain limit, the total number of chips on each burn-in board must be decreased as the maximum, power dissipation per chip increases.
Still another limitation of the chip testing system in patent '129 is that the stored test data patterns in the large SRAM
145
on each driver board can make very inefficient use of the SRAM memory cells.
FIG. 9
of patent 3 129 shows that each SRAM
145
receives nineteen address bits and has eight data output bits; and thus the SRAM
145
on each driver circuit has eight million memory cells. But, certain types of chips are tested by sending them sequences of serial bit streams that vary in number with time. Thus, if an SRAM
145
sends four bit streams during one time interval and sends only two bit streams during other time intervals, then half of the SRAM is wasted when the two bit streams are being sent.
Accordingly, a primary object of the chip test testing system which is disclosed herein is to address and overcome all of the above limitations.
BRIEF SUMMARY OF THE INVENTION
The present invention, as recited by the claims, covers one aspect of the disclosed chip testing system which addresses the above limitation regarding inefficient storage of the test data patterns. In accordance with the present invention, a system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary.
If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. Consequently, the only memory cells that are wasted are those which store the unused bits after each bit stream. But, those unused bits cause the next bit stream to start on a word boundary; and, that simplifies the circuitry which the pattern generator uses to address each bit stream.
REFERENCES:
patent: 5867723 (1999-02-01), Chin et al.
patent: 6173238 (2001-01-01), Fujisaki
patent: 6205567 (2001-03-01), Maruyama
patent: 6233182 (2001-05-01), Satou et al.
patent: 6237122 (2001-05-01), Maki
Barr Timothy Allen
Conklin Robert David
Rhodes James Vernon
Fassbender Charles J.
Hoff Marc S.
Kim Paul
Rode Lise A.
Starr Mark T.
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