Program section layout method and layout program

Details Program section layout method and layout program Program section layout method and layout program

2011-06-28

2011-06-28

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S129000, C711S133000, C711S136000, C711S173000, C711SE12046, C711SE12072, C717S151000

Reexamination Certificate

active

07970997

ABSTRACT:
A program section layout method capable of improving space efficiency of a cache memory. A grouping unit groups program sections into section groups so that the total size of the program sections composing each section group does not exceed cache memory size. A layout optimization unit optimizes the layout of section group storage regions by combining each section group and a program section that does not belong to any section groups or by combining section groups while keeping the ordering relations of the program sections composing each section group.

REFERENCES:
patent: 6678886 (2004-01-01), Kumon
patent: 2004/0098541 (2004-05-01), Megiddo et al.
Keisuke Hashimoto, et al., “Basic-Block-Level Code Placement to Reduce Instruction Cache Misses”, Joint Symposium on Parallel Processing JSPP'99, Information Processing Society of Japan, Jun. 9, 1999, vol. 99, No. 6, pp. 31-28.
Japanese Office Action issued on Apr. 14, 2009 in corresponding Japanese Patent Application 2004-262490.
Patent Abstracts of Japan, Publication No. 2000-056983, Published Feb. 25, 2000.
Patent Abstracts of Japan, Publication No. 2000-267861, Published Sep. 29, 2000.
Patent Abstracts of Japan, Publication No. 2001-216140, Published Aug. 10, 2001.

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