Program methods for split-gate memory

Details Program methods for split-gate memory Program methods for split-gate memory

2006-09-20

2009-02-24

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185230, C365S185330

Reexamination Certificate

active

07495960

ABSTRACT:
An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.

REFERENCES:
patent: 5966331 (1999-10-01), Shiau et al.
patent: 5978277 (1999-11-01), Hsu et al.
patent: 6005809 (1999-12-01), Sung et al.
patent: 6233177 (2001-05-01), Shokouhi et al.
patent: 7342828 (2008-03-01), Ishii et al.

Affiliated with

Also associated with

Rating

Program methods for split-gate memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Program methods for split-gate memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Program methods for split-gate memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4073728