Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-08-01
2010-10-19
Maskulinski, Michael C (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
07818620
ABSTRACT:
A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU forced stop signal between an ICE device and the CPU is considered and set, and a CPU forced stop signal issuance position which is prior to a stop target position is determined. Based on a real-time tracing function of the CPU, at an issuance position and timing of the CPU forced stop signal on the execution of the program, the CPU forced stop signal is issued, the CPU is stopped, and the event is acquired. By this means, an arbitrary number of events of the program can be acquired regardless of the number of breakpoint registers.
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Nagano Takehiko
Nojiri Toru
Shigeoka Tomohiko
Antonelli, Terry Stout & Kraus, LLP.
Hitachi , Ltd.
Maskulinski Michael C
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