Program counter (PC) relative addressing mode with fast...

Details Program counter (PC) relative addressing mode with fast... Program counter (PC) relative addressing mode with fast...

2006-02-21

2006-02-21

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S230000

Reexamination Certificate

active

07003651

ABSTRACT:
The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

REFERENCES:
patent: 5608886 (1997-03-01), Blomgren et al.
patent: 6044455 (2000-03-01), Hara
patent: 6237087 (2001-05-01), O'Connor
patent: 6243805 (2001-06-01), Mahurin
patent: 6502185 (2002-12-01), Keller et al.
SuperH™ RISC Engine SH-4, Programming Manual, Hitachi, Ltd. Apr. 19, 2001, pp. 199, 10-22.
Linley Gwennap, “MAJC Gives VLIW a New Twist”, Microdesign Resources, Sep. 13, 1999; Microprocessor Report, pp. 12-15, 22.

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