Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-02-20
2001-11-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06320802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a program circuit capable of recording data in a non-volatile manner and a configuration of a semiconductor memory device using the same program circuit. More particularly, the present invention relates to a program circuit that is applied to a semiconductor memory device including a redundant circuit and a configuration of a semiconductor memory device having such a program circuit.
2. Description of the Background Art
FIG. 17
is a block diagram showing a configuration of a main portion of a conventional semiconductor memory device that includes a redundant circuit.
A memory cell array
1
includes a plurality of word lines WL, a plurality of bit line pairs BL crossing the plurality of word lines WL, and a plurality of memory cells MC provided at the respective crossing points of word lines WL and bit line pairs BL. Memory cell array
1
further includes a redundant word line RWL and a plurality of memory cells MC connected to the redundant word line RWL.
A decoder
2
and a sense amplifier unit
13
are connected to memory cell array
1
. Sense amplifier unit
13
includes a plurality of sense amplifiers connected to the plurality of bit line pairs BL, a plurality of transfer gates, and a decoder.
This semiconductor memory device is provided with a replacement circuit
10
. Replacement circuit
10
includes a redundancy select circuit
3
, a replacement address program circuit
4
and a NAND circuit
5
. Replacement circuit
10
and redundant word line RWL constitute a redundancy circuit.
An operation of the semiconductor memory device shown in
FIG. 17
will now be described.
Decoder
2
responds to an X address signal XA and selects one of the plurality of word lines WL within memory cell array
1
, and raises the potential of the selected word line WL to an H level. Thus, data are read out from memory cells MC connected to the selected word line WL to corresponding bit line pairs BL. The data thus read out are amplified by the sense amplifiers provided in sense amplifier unit
13
. The decoder in sense amplifier unit
13
responds to a Y address signal YA and renders one of the plurality of transfer gates conductive. As a result, one piece of data is output.
If there is a defect associated with a certain word line WL, redundant word line RWL is used instead of that word line WL. In this case, the output of redundancy select circuit
3
attains an H level. An address of the word line WL to be replaced is programmed in replacement address program circuit
4
.
If an address designated by X address signal XA matches the address (replacement address) programmed in replacement address program circuit
4
, then the output of replacement address program circuit
4
attains an H level. When the outputs of redundancy select circuit
3
and replacement address program circuit
4
both attain an H level, the output of NAND circuit
5
(a decoder inactivation signal DA) attains an L level. Thus, the decoder becomes inactive, and all the word lines WL enter an unselected state. The potential of redundant word line RWL rises to an H level.
Thus, in response to a defective word line WL or a word line WL connected to a defective memory cell MC having been selected, redundant word line RWL is selected instead of the word line WL.
Although not shown in
FIG. 17
, memory cell array
1
may include a redundant bit line pair.
FIG. 18
is a circuit diagram illustrating a configuration of a fuse program circuit
810
included in redundancy select circuit
3
.
Referring to
FIG. 18
, fuse program circuit
810
includes a fuse element F
1
provided between a node N
1
and a power supply potential Vcc; a MOS capacitor C
1
provided between node NI and a ground potential GND; an N channel MOS transistor QN
1
provided between node N
1
and a ground potential GND; and an inverter INV
1
that receives and inverts the potential of node N
1
and supplies its output to a gate of transistor QN
1
.
The potential at an output node N
2
of inverter INV
1
becomes an output level of fuse program circuit
810
, and this output level in turn becomes an output level of redundancy select circuit
3
. Thus, the output level of fuse program circuit
810
is at an L level when a fuse is not blown and at an H level when the fuse is blown.
In a normal mode, i.e., when redundant word line RWL is not in use (referred to as a “redundancy non-selected mode”), fuse F
1
is connected. Thus, the potential of node N
2
is at a ground level, and a signal of an L level is input to NAND circuit
5
in FIG.
17
. As a result, decoder inactivation signal DA attains an H level, and the potential of redundant word line RWL remains inactive.
When redundant word line RWL is to be used (referred to as a “redundancy selected mode”), fuse F
1
is blown. At power-on, the potential of node N
2
starts to rise towards an H level because of capacitive coupling by the MOS capacitor C
1
. Further, the potential of node N
2
reaches a complete H level by a positive feedback circuit consisting of transistor QN
1
and inverter INV
1
.
Accordingly, in the redundancy non-selected mode, the output of redundancy select circuit
3
attains an L level; whereas, in the redundancy selected mode, it attains an H level.
FIG. 19
is a circuit diagram illustrating a detailed configuration of replacement address program circuit
4
. An address setting circuit
40
includes a fuse F
11
, a MOS capacitor C
11
, an N channel MOS transistor QN
11
and an inverter INV
11
. An address setting circuit
50
includes a fuse F
12
, a MOS capacitor C
12
, an N channel MOS transistor QN
12
and an inverter INV
12
. The configuration and operation of each of address setting circuits
40
and
50
are similar to those of fuse program circuit
810
included in redundancy select circuit
3
shown in FIG.
18
.
Thus, the potential at node N
21
of address setting circuit
40
attains an L level when fuse F
11
is connected and an H level when fuse F
11
is blown. Similarly, the potential at node N
22
of address setting circuit
50
is at an L level when fuse F
12
is connected and at an H level when fuse F
12
is blown.
Between an input terminal I
1
and an output terminal O
1
are connected P channel transistors
61
,
62
and N channel transistors
71
,
72
. Similarly, P channel transistors
63
,
64
and N channel transistors
73
,
74
are connected between an input terminal I
2
and output terminal O
1
; P channel transistors
65
,
66
and N channel transistors
75
,
76
, between an input terminal I
3
and output terminal O
1
; and P channel transistors
67
,
68
and N channel transistors
77
,
78
, between an input terminal I
4
and output terminal O
1
.
The gate electrodes of transistors
61
,
73
,
65
,
77
are connected to node N
21
of address setting circuit
40
. The gate electrodes of transistors
71
,
63
,
75
,
67
are connected to node N
1
of address setting circuit
40
. The gate electrodes of transistors
62
,
64
,
76
,
78
are connected to node N
22
of address setting circuit
50
. And the gate electrodes of transistors
72
,
74
,
66
,
68
are connected to node N
12
of address setting circuit
50
.
Pre-decode signals, obtained by pre-decoding X address signals XA, are programmed in replacement address program circuit
4
shown in FIG.
19
. The way of programming in program circuit
4
will now be described.
First, pre-decode signals X
0
·X
1
, X
0
·/X
1
, /X
0
·X
1
, /X
0
·/X
1
are defined as follows:
If X
0
=H level and X
1
=H level, then X
0
·X
1
=H level;
If X
0
=H level and X
1
=L level, then X
0
·/X
1
=H level;
If X
0
=L level and X
1
=H level, then /X
0
·X
1
=H level; and
If X
0
=L level and X
1
=L level, then /X
0
·/X
1
=H level.
Under the conditions other than the above, pre-decode signals X
0
·X
1
, X
0
·/X
1
, /X
0
·X
1
and /X
0
·/X
1
each attain an L level.
Here, assume that pre-decode signal X
0
·X
1
is applied to input terminal I
1
, pre-decode signal
Elms Richard
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Phung Anh
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