Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-11-06
2009-02-24
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185050
Reexamination Certificate
active
07495958
ABSTRACT:
An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.
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Cho, M. K., et al., “High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology,” IEEE Electron Device Letters, Aug. 2000, pp. 399-401, vol. 21, No. 8, IEEE.
Silicon Storage Technology, Inc., “Technology Comparison of Floating Gate Reprogrammable Nonvolatile Memories,” Technical Paper, Nov. 2001, 8 pages, Silicon Storage Technology, Inc., Sunnyvale, CA.
Hoang Huan
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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