Production of two superposed elements within an integrated...

Details Production of two superposed elements within an integrated... Production of two superposed elements within an integrated...

2006-05-26

2010-06-15

Chea, Thorl (Department: 1795)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S313000, C430S314000, C430S320000

Reexamination Certificate

active

07736840

ABSTRACT:
A first circuit element, which is reflective, is formed. A first layer, which is attenuating, is formed. above the first circuit element. A second layer, which is transparent, is formed above the first layer to fill an aperture in the first layer. An overlying lithography resist layer is then exposed to a radiation flux level below a development threshold but high enough that a sum of the radiation flux level and a reflected secondary radiation flux level exceeds the development threshold. The lithography resist layer is developed so as to obtain a mask having an opening through which the first and second layers are removed to form a second aperture which is filled to form a second circuit element.

REFERENCES:
patent: 5981150 (1999-11-01), Aoki et al.
patent: 6080654 (2000-06-01), Manchester
patent: 6756286 (2004-06-01), Moriceau et al.
patent: 2003/0042627 (2003-03-01), Farrar et al.
patent: 2004/0104448 (2004-06-01), Marty et al.
patent: 2005/0176222 (2005-08-01), Ogura
patent: 2005/0208696 (2005-09-01), Villa et al.
patent: 2005/0287767 (2005-12-01), Dantz et al.
patent: 0 967 641 (1999-12-01), None
Patent Abstracts of Japan, vol. 1998, No. 6, Apr. 30, 1998 & JP 10 041207 A (Toshiba Corp), Feb. 13, 1998.
Tsutomu Sato, et al., “A New Substrate Engineering for the Formation of Empty Space in Silicon (ESS) Induced by Silicon Surface Migration;” IEEE No. 0-7803-5413-3, 1999.
Akito Hara, et al., “Self-Aligned Top and Bottom Metal Double Gate Low Temperature Poly-Si TFT Fabricated at 550°C. on Non-Alkali Glass Substrate by Using DPSS Cw Laser Lateral Crystallization Method,” IEEE No. 0-7803-7873-3, 2003.
Preliminary French Search Report, FR 05 05880, dated Feb. 17, 2006.
Sato, et al., “A New Substrate Engineering for the Formation of Empty Space in Silicon (ESS) Induced by Silicon Surface Migration,” Electron Devices Meeting, 1999; IEDM Technical Digest, International Washington, DC, USA, Dec. 5-8, 1999; Piscataway, NJ, USA, IEEE, US, Dec. 5, 1999, pp. 517-520; XP010372210; ISBN: 0-7803-5410-9.
Sato, et al., “SON (Silicon on Nothing) MOSFET using Ess (Empty Space in Silicon) Technique for SoC Applications,” International Electron Devices Meeting 2001; IEDM; Technical Digest, Washington, DC, Dec. 2-5, 2001, New York, NY; IEEE, US Dec. 2, 2001, pp. 37.1.1-37.1.4; XP010575245; ISBN 0-7803-7050-3.

Affiliated with

Also associated with

Rating

Production of two superposed elements within an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Production of two superposed elements within an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Production of two superposed elements within an integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4237214