Production method for silicon epitaxial wafer and silicon...

Details Production method for silicon epitaxial wafer and silicon... Production method for silicon epitaxial wafer and silicon...

2001-07-10

2003-07-08

Kunemund, Robert (Department: 1765)

Single-crystal, oriented-crystal, and epitaxy growth processes;

Forming from vapor or gaseous state

With decomposition of a precursor

C117S095000, C117S101000, C117S105000, C117S089000, C117S935000

Reexamination Certificate

active

06589336

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for producing silicon epitaxial wafer, and epitaxial wafer produced by such method; and in particular to a method for producing silicon epitaxial wafer in which a silicon epitaxial layer is ion-implanted and is then stacked with another silicon epitaxial layer by vapor-phase growth, to thereby form a buried layer, and epitaxial wafer produced by such method.
DESCRIPTION OF THE BACKGROUND ART
Japanese Laid-Open Patent Publication 1-105557 discloses a technique in which an impurity element is introduced by ion implantation into a silicon single-crystalline thin film (simply referred to as “silicon epitaxial layer”, or more simply as “epitaxial layer” hereinafter) in a silicon epitaxial wafer (simply referred to as “epitaxial wafer” hereinafter) which comprises a silicon single-crystalline substrate and such epitaxial layer formed thereon by the vapor-phase epitaxial growth process. The above publication also discloses process steps for fabricating a CMOS circuit in such epitaxial wafer.
In the fabrication of a vertical MOSFET or vertical bipolar transistor in the epitaxial wafer, it is sometimes necessary to form an impurity doped region having a large depth (which is referred to as “vertical doped region” or “vertical impurity-doped region” hereinafter in this specification). Such “vertical doped region” is typified by a device isolation region for isolating a device from other region (device isolation regions 3, 4 in FIG. 1 of the above patent publication), and an impurity-doped region serving as a conduction route toward a high-density impurity diffused layer formed so as to be buried in the wafer (drain regions 6, 6a in FIG. 1 of the above patent publication).
For the case that the epitaxial layer is formed as a single layer having a relatively large thickness, it may be rather difficult to form a vertical doped region deep enough to penetrate the epitaxial layer only by a direct ion implantation. One technique for solving such problem is such that preliminarily forming an ion-implanted layer in the surface region of the substrate, growing thereon the epitaxial layer, forming another ion-implanted layer in the surface region of such epitaxial layer, and annealing the substrate so as to diffuse the doped impurity to thereby joint both ion-implanted layers produced by such ion implantations conducted twice. Such method is, however, still disadvantageous in terms of downsizing of the device for the case the vertical diffusion length is considerably large, since such case also requires a sufficient margin for the lateral diffusion. The foregoing patent publication also discloses a technique in which the formation process of a relatively thin epitaxial layer is repeated in plural times, rather than forming a single epitaxial layer which is relatively thick, where the individual formation processes of the epitaxial layers include doping of an impurity in a predetermined region, and perform annealing for diffusion so as to allow the individual impurity-doped regions to overlap with each other from the last epitaxial layer to a desired depth. It is described in the patent publication that such technique is advantageous in that the process only requires a short vertical diffusion length since the ion-implanted layer is provided to every epitaxial layer having a relatively small thickness, which successfully suppresses the lateral diffusion, and shortens the annealing time.
Now in the technique disclosed in the foregoing patent publication, an oxide film formed on the epitaxial layer is used as a mask (referred to as “ion implantation mask oxide film” hereinafter) for allowing selective implantation of impurity ion into a specific region in the epitaxial layer. Since the ion implantation mask is formed by thermal oxidation of the surface of the epitaxial layer, so that forming the ion-implanted layer into every epitaxial layer inevitably causes thermal history due to the oxide film formation in the number of repetition same with the number of the epitaxial layers (a first thermal history).
Annealing is also required after the ion implantation in order to recover crystal damage (referred to as “crystal recovery annealing” hereinafter), since crystal damage (defect) inevitably occurs due to the ion implantation effected at a high energy, so that the thermal history due to such annealing will be also added in the number of times same with the repetitive, number of the ion implantation (a second thermal history). In addition, if the surface in the pattern opening exposed after removal by etching of the ion implantation mask oxide film is directly implanted with ion and then annealed for crystal recovery (generally proceeded in an inert atmosphere such as in a nitrogen atmosphere), such surface tends to roughen due to such ion implantation as shown in FIG.
12
A. Thus it is a general practice to form, prior to the ion implantation, a thin oxide film for preventing the surface roughening on the surface of the epitaxial layer exposed by the etching as shown in
FIG. 12B
(so-called pre-implantation oxidation). The formation of such oxide film is accomplished by thermal oxidation, which is again causative of thermal history in the number of times same with the repetitive number of the ion implantation (a third thermal history). Such ion-implanted layer is further stacked with another epitaxial layer grown thereon by the vapor-phase growth process to thereby form a buried layer, where high temperature during the process will be still again causative of thermal history in the number of times same with the repetitive number of epitaxial layers (a fourth thermal history).
Thus in the technique described in the foregoing patent publication, the ion-implanted layers are repetitively affected by four such types of thermal histories in each process cycle comprising the formation of the epitaxial layer and the ion implantation, so that the vertical doped region formed based on such ion-implanted layers cannot always be controlled in terms of diffusion in the lateral direction. For example, as shown in
FIG. 6A
, for the case that ion-implanted layers
101
,
102
are formed between each adjacent epitaxial layers
103
a
to
103
c,
diffused regions
101
a,
102
a
already expand to a considerable degree by the time that the formation of the epitaxial layers
103
a
to
103
c
and ion-implanted layers
101
,
102
is completed due to multiple times of thermal history. If the annealing for diffusion is further proceeded to allow the individual ion-implanted layers
101
,
102
to diffuse in the vertical direction and to joint with each other to thereby form a vertical doped region
105
, the individual portions
105
a
,
105
b
corresponded to the ion-implanted layers
101
,
102
will show a large lateral expansion. In particular, the lower ion-implanted layer
101
results in a larger lateral expansion as compared with the upper ion-implanted layer
102
, since the former is affected by the repetitive thermal history with a larger number of times.
More specifically, as shown in
FIG. 6C
, an ion-implanted layer
101
will have a larger degree of the lateral expansion as the position thereof becomes lower, and the layers (in particular in the lower positions) will already be jointed to a certain degree due to the vertical diffusion by the time the top ion-implanted layer is formed. Thus the vertical doped region
105
obtained after the successive annealing will be only such that having a non-uniform width which grows toward the bottom as shown in FIG.
6
D. For the case the ion-implanted layers of different conduction types (n-type and p-type, for example) have to be formed in the same epitaxial layer, it is necessary to repeat a process cycle, comprising the formation of the ion implantation mask oxide film, the pre-implantation oxidation and the crystal recovery annealing, for each conduction type, which will worsen the situation.
Another problem resides in the technique disclosed in Japanese Laid-Open Patent Publication 1-105557, in

Affiliated with

Also associated with

Rating

Production method for silicon epitaxial wafer and silicon... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Production method for silicon epitaxial wafer and silicon..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Production method for silicon epitaxial wafer and silicon... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3059021