Procss for fabricating a ferroelectric capacitor in a semiconduc

Details Procss for fabricating a ferroelectric capacitor in a semiconduc Procss for fabricating a ferroelectric capacitor in a semiconduc

1992-12-21

1993-11-02

Dang, Thi

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156651, 156652, 156656, 156664, 252 792, 252 793, 134 3, 134 41, H01L 2100

Patent

active

052580938

ABSTRACT:
An etching process for the patterning of electrodes and a ferroelectric dielectric layer in a ferroelectric capacitor, which is formed in a semiconductor device, is disclosed. A series of overlying layers including a first electrode layer (16), a ferroelectric layer (18), and a second electrode layer (20) are etched to form a ferroelectric capacitor (14) on a semiconductor substrate (10). The second electrode layer (20) is selectively etched in a first aqueous solution containing hydrochloric acid, nitric acid, and a metal etching compound comprised of phosphoric acid, nitric acid, and acetic acid. The ferroelectric layer (18) is selectively etched in a second aqueous solution containing hydrogen peroxide, hydrofluoric acid, and nitric acid. The etch rate of the ferroelectric layer in the second aqueous solution is controlled by selection of the relative concentration of the chemicals used to form the solution. The wet chemical etching process of the invention can be combined with a dry etching process for the purpose of removing dry etch residue following formation of the ferroelectric capacitor (14).

REFERENCES:
patent: 5164808 (1992-11-01), Evans, Jr. et al.
patent: 5189594 (1993-02-01), Hoshiba
patent: 5206788 (1993-04-01), Larson et al.
Trolier, et al., "Etched Piezoelectric Structures", IEEE Proceedings International Symposium on Applications of Ferroelectrics, 1986, pp. 707-710.
Toyama, et al., "Crack-Free PZT Thin Films Micropatterned On Silicon Substrate For Integrated Circuits", ISIF 3rd Int. Sym. Integ. Ferroelectrics, Apr. 3-5, 1991, pp. 444-447.
Rod, "Process Issues in the Development of a Ferroelectric Capacitor/CMOS Test Chip" Rep. No. HDL-PR-91-2, Dec., 1991, U.S. Army Laboratory Command, Adelphi, Md.

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