Processor with short set-up and hold times for bus signals

Details Processor with short set-up and hold times for bus signals Processor with short set-up and hold times for bus signals

1998-10-07

2000-04-04

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

713400, G06F 106, G06F 112

Patent

active

060473827

ABSTRACT:
A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.

REFERENCES:
patent: 5036230 (1991-07-01), Bazes
patent: 5371416 (1994-12-01), Atriss et al.
patent: 5450458 (1995-09-01), Price et al.
patent: 5471587 (1995-11-01), Fernando
patent: 5485602 (1996-01-01), Ledbetter, Jr. et al.
patent: 5535377 (1996-07-01), Parks
patent: 5634116 (1997-05-01), Singer
patent: 5914996 (1999-06-01), Huang

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