Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-12-14
2004-08-31
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C714S013000, C711S125000, C711S169000
Reexamination Certificate
active
06785841
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention is related to the field of semiconductor devices and more particularly to a microprocessor device that incorporates redundant circuitry suitable for replacing defective portions of the processor.
2. History of Related Art
In the field of semiconductor devices, manufacturing yield is a critical factor determining the profitability of a particular device. Manufacturing yield refers to the percentage of die on a wafer that are fully functional. Typically the yield of a given device or technology is a strong function of particle count in the fabrication facility. Particles may produce tiny defects in one or more layers of the device. As the particle count increases, the manufacturing yield drops correspondingly.
Typically, the defects caused by particles are extremely localized. A particle may, for example, result in a tiny short circuit between adjacent metal lines. In such cases, the vast majority of the device is free of defects and fully functional. In the absence of the ability to correct or circumvent the failure caused by the defect, however, the device is non-functional.
Manufacturers have attempted to improve yield through the use of redundancy. Redundancy refers to the practice of designing spare circuits or features designed into a semiconductor device or integrated circuit. Under appropriate circumstances, the redundant feature or features may replace a similar feature in the device to produce a fully functional device.
Redundancy is most commonly associated with integrated circuits that include large sections of highly repetitive circuitry. As an example, memory devices, which typically include a large array of memory cells arranged as a series of rows and columns, are ideally suited for beneficially implementing redundant elements. Spare rows and columns are designed into the device. If the device is fully functional, the spare rows and columns are not used. If one or more rows and columns are defective, the defective elements may be disabled and the spare elements enabled to provide functionally equivalent substitutes.
Although redundancy has been used advantageously in semiconductor memories, it has not been as successfully implemented in logic devices such as microprocessors. Processors characteristically include a number of distinct functional elements that lack the symmetry and homogeneity of a memory cell array. While entire functional elements could be replicated to provide redundant capability, the resulting increase in die size would substantially offset the benefit provided.
As an example, most processors include one or more load/store units that enable the processor to retrieve information from and store information to memory. The load/store unit design is distinct from the design of other functional units such as a fixed point arithmetic unit, a floating point unit, or a branch unit. While a redundant load/store unit could be included in the design of a processor, the processor die size would increase substantially thereby reducing the number of devices on a wafer. Moreover, the utility of the redundant load/store unit is significantly limited. More specifically, the redundant load/store unit is only beneficial when the original load/store unit is the functional unit that prevents the device from being fully functional. If the load/store unit occupies 20% or less of the device, the probability that a device with a single, randomly located defect is repairable may not justify the inclusion of the redundant element in the design.
Thus, for conventionally designed processor chips, redundancy has typically not been used with great success. It would be desirable, therefore, to design a processor device with cost effective redundant elements.
SUMMARY OF THE INVENTION
The problem identified above is in large part addressed by a system that includes a central processor and a plurality of attached processors. In one embodiment, the central processor may comprise a general purpose CPU and each of the attached processors provides support functions for the CPU. Each of the attached processors may comprise a single instruction multiple data (SIMD) processor such as a vector processor or an array processor. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be identical or substantially equivalent to each of the attached processors. In one embodiment, each of the attached processors is associated with an attached processor ID. Attached processor instructions may include ID information that is used to execute each attached processor instruction selectively in the appropriate attached processor. The attached processor ID may be specified in a programmable ID register of each of the attached processor. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. Disabling the non-functional processor may include altering the information in the attached processor ID register while enabling the redundant processor may include programming the processor ID of the redundant processor to the value of the non-functional processor. Disabling the non-functional attached processor may further include electrically disconnecting the attached processor such as by destroying one or more fuseable links.
REFERENCES:
patent: 5815651 (1998-09-01), Litt
patent: 6173416 (2001-01-01), Liddell et al.
patent: 6435712 (2002-08-01), Ota
Akrout Chekib
Hofstee Harm Peter
Kahle James Allan
Euripidou Christopher
Iqbal Nadeem
Lally Joseph P.
Salys Casimer K.
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