Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1997-10-29
2001-12-04
Beausoleil, Robert (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S310000, C713S323000, C713S340000
Reexamination Certificate
active
06327665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor with a power consumption limiting function and, more particularly, a power consumption controlling technique for the processor capable of avoiding, regardless of behavior of a program to be executed, that a quantity of generated heat due to power consumption exceeds a predetermined level.
2. Description of the Prior Art
A conceptual view illustrating a configuration of a processor is shown in FIG.
1
. The processor normally executes following operations. First an instruction designated by a program counter
43
is reads from an instruction memory
45
, and then the contents of such instruction are converted into a control signal by an instruction decoder
51
.
Data are read from a register or a main memory
41
according to the contents of the instruction. The data are then processed by arithmetic units which take charge of execution of the instruction. Processed results are then stored in the register or the memory.
In this case, the contents of the main memory is often cached into a high speed and small capacity memory (cache memory). In many cases, the memory which is accessed by the processor in operation signifies this cache memory.
In the event that the processor has to be constituted, taking account of these operations, it is almost indispensable to constitute mechanisms for executing respective functions as modules. As examples of such modules, there are arithmetic units such as ALU, functional blocks such as cache memory, general purpose register, etc., pipeline control logic circuits, and soon. Needless to say, there can be thought of various ways to classify the modules. Normally such modules are designed to have such a hierarchical structure that respective modules are constituted of smaller modules to take charge of smaller functions and operations. Thus it can be said in other words that
FIG. 1
represents signals and data streams among the modules.
In the recent processors, a modular structure of a digital signal processor (abbreviated as “DSP” hereinafter) has been implemented. In particular, a number of microprocessors having the DSP function to deal with image data have been developed in recent years. In general, such DSP arithmetic unit having the DSP function has a high arithmetic performance to thus consume high electric power in its arithmetic operation (i.e., in operation). This is because, since generally arithmetic units having the higher arithmetic performance within the same number of cycle are designed to have a larger circuit scale, loads to be charged/discharged during operation become larger in size correspondingly.
Normally these DSP arithmetic units (for example, product-sum arithmetic unit, etc.) consume extremely high electric power compared to the arithmetic units (such as ALU, branch unit, etc.) installed in the microprocessor. Accordingly, in such microprocessors, power consumption of the overall processor is increased higher if the number of operation of these DSP arithmetic units is increased much more, while power consumption of the overall processor is decreased lower if the number of operation of these DSP arithmetic units is decreased much less.
Therefore, in the microprocessor including these DSP arithmetic units mixedly, power consumption is largely different according to a frequency of occurrence of the DSP instruction in the program to be executed, for the number of operation (frequency of operation, activation yield) of the DSP arithmetic units per unit time is largely varied during operation of the microprocessor according to such frequency of occurrence of the DSP instruction.
In fact, in the event that an image processing program to decompress compressed data is executed with the use of the DSP instruction, power consumption is required several times rather than that required when the program without the DSP instruction is executed.
The activation yield and the power consumption will then be mentioned hereunder. Present processors are often composed of potential transmitting devices. In such potential transmitting devices, power consumption is mainly caused because of charge/discharge of the loads in the circuit. Such power consumption will be explained with referring to a MOS device shown in
FIG. 2
as an example.
In
FIG. 2
,
63
,
67
denote a PMOS respectively;
65
,
69
, an NMOS respectively; and
71
, a capacitance which is parasitic on wirings, etc. Suppose that, in an initial state, a node
73
is set to the same potential as Vss, the PMOS
63
is in its OFF state, and the NMOS
65
is in its ON state. A current seldom flows in this state and therefore power consumption appears only to such an extent that it can be ignored.
Assume now that the PMOS
63
and the NMOS
65
are switched so that the PMOS
63
is turned to its ON state and the NMOS
65
is turned to its OFF state. Electric currents flow from Vcc to the capacitance
71
, a gate capacitance of the PMOS
67
, and a gate capacitance of the NMOS
69
via the PMOS
63
which has been ONed. At this time, electric power is consumed. Accordingly, the node
73
which has been at the same potential as Vss in the initial state can be charged up to Vcc by the currents. When the node
73
has been charged up to Vcc, the currents can be reduced to such an extent that they can be ignored (The major cause why such currents do not completely become zero is presence of a leakage current of the transistor). After the node
73
has been charged up to Vcc, similarly the power consumption can be reduced to such an extent that it can be ignored.
In this fashion, in the above potential transfer devices, power consumption is generated mainly due to charge/discharge of the load in the circuit. In other words, such power consumption is generated by switching the current sources to drive the load node (e.g., PMOS, NMOS in the above example). If there is no switching operation, power consumption is extremely small. Hence, the power consumption which is consumed by a certain load for a certain time is in proportion to how many times the load is charged/discharged for the certain time, i.e., how many times the driving sources are switched to charge/discharge the load. That is to say, the power consumption which has been consumed by the certain load for the certain time is proportional to the activation yield of the load within the certain time.
With the above configuration, the power consumption of the overall processor for the certain time can be derived by adding products of the magnitude of the load of the node and the activation yield of the node (i.e., power consumption at the node) for all nodes.
Since the processor is composed of a plurality of modules, power consumption of an overall processor can be detected by calculating a sum of power consumption at respective nodes module by module and then adding such sums for all modules.
In the prior art processor, under the assumption that several typical programs can be supposed, the activation yields of respective arithmetic units have been estimated and then an average power consumption of the overall microprocessor has been estimated based on the estimated activation yields. A product of the power consumption and an operation time can yield generated heat in the processor for the operation time. A package of the processor, if selected from a viewpoint of heat resistance, has been selected based on such generated heat. A mechanism for monitoring an operation state of the processor has not been installed in the processor itself.
In the above case, the package has been selected such that an expensive high heat-resistant package is employed so as to mate with peak power, or else an inexpensive low heat-resistant package is employed so as to mate with average power consumption.
However, in the case that the former package is employed and also the average power is small, package cost is of no use when the processor is being operated at the average power. Conversely, in the case of the latter package, the program has to assure that gener
Beausoleil Robert
Foley & Lardner
Kabushiki Kaisha Toshiba
Vo Tim
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