Processor with multiple linked list storage feature

Details Processor with multiple linked list storage feature Processor with multiple linked list storage feature

2006-10-24

2006-10-24

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S127000, C711S157000, C365S230030, C365S230040

Reexamination Certificate

active

07127547

ABSTRACT:
A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list data structures are stored in memory circuitry associated with the processor, and the memory circuitry is arranged in a plurality of banks. The plurality of banks are configured to store respective ones of the plurality of separate linked list data structures, such that each of the plurality of banks stores a corresponding one of the plurality of separate linked list data structures. The linked list data structures are accessed in an alternating manner that reduces the likelihood of access conflicts between the banks. The processor may be configured as a network processor integrated circuit to provide an interface between a network and a switch fabric in a router or switch.

REFERENCES:
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U.S. Appl. No. 10/630,961, filed Jul. 30, 2003, R.A. Corley et al., “Processor Configured for Efficient Processing of Single-Cell Protocol Data Units.”
U.S. Appl. No. 10/025,331, filed Dec. 19, 2001, G.A. Bouchard et al., “Dynamic Random Access Memory System with Bank Conflict Avoidance Feature.”

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