Processor with instruction-based interrupt handling

Details Processor with instruction-based interrupt handling Processor with instruction-based interrupt handling

2004-04-28

2010-11-09

An, Meng-Ai (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

Reexamination Certificate

active

07831979

ABSTRACT:
A processor comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is operative to retrieve from the memory circuitry an interrupt polling instruction which causes selection of an active enabled interrupt and generation of an interrupt vector for the selected active enabled interrupt. In conjunction with the selection and generation operations, an execution context of a program thread is stored in the memory circuitry, the stored execution context being utilizable to resume the program thread at an appropriate time subsequent to interruption of that thread.

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