Processor with an addressable address translation buffer operati

Details Processor with an addressable address translation buffer operati Processor with an addressable address translation buffer operati

1995-09-07

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

365 49, G60F 1202

Patent

active

058359630

ABSTRACT:
A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

REFERENCES:
patent: 4580240 (1986-04-01), Watanabe
patent: 5299147 (1994-03-01), Holst
patent: 5375216 (1994-12-01), Moyer
patent: 5454091 (1995-09-01), Sites
patent: 5539892 (1996-07-01), Reininger
patent: 5606687 (1997-02-01), Mehring

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