Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1997-01-23
2000-01-11
Amsbury, Wayne
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
711200, G06F 1730
Patent
active
060147237
ABSTRACT:
An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element. A first comparison element compares the value of the referenced element and the maximum array index boundary value and provides a maximum violation signal if the value of the element is greater than the maximum array size boundary value. A second comparison element compares the value of the element and the minimum array size boundary value and provides a minimum violation signal if the value of the element is less than the minimum array bounds value. Either a maximum violation signal or a minimum violation signal results in an exception.
REFERENCES:
patent: 3905023 (1975-09-01), Perpiglia
patent: 4079453 (1978-03-01), Dahl
patent: 4084225 (1978-04-01), Anderson et al.
patent: 4905188 (1990-02-01), Chuang et al.
patent: 5014235 (1991-05-01), Morton
patent: 5146592 (1992-09-01), Pfeiffer et al.
patent: 5341483 (1994-08-01), Frank et al.
patent: 5373290 (1994-12-01), Lempel et al.
patent: 5583988 (1996-12-01), Crank et al.
patent: 5644709 (1997-07-01), Austin
patent: 5777608 (1998-07-01), Lipovski et al.
patent: 5835963 (1998-11-01), Yoshioka et al.
Joy William N.
O'Connor James Michael
Tremblay Marc
Amsbury Wayne
Gunnison Forrest
Sun Microsystems Inc.
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