Telecommunications – Transmitter and receiver at same station – Radiotelephone equipment detail
Reexamination Certificate
1998-10-01
2001-02-06
Hunter, Daniel S. (Department: 2749)
Telecommunications
Transmitter and receiver at same station
Radiotelephone equipment detail
C455S073000
Reexamination Certificate
active
06185438
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to wireless communication networks and, more specifically, to a processor that uses a virtual buffer descriptor array to control communication ports of the processor.
BACKGROUND OF THE INVENTION
Reliable predictions indicate that there will be over 300 million cellular phone customers by the year 2000. In the U.S., cellular service is offered not only by dedicated cellular service providers, but also by the regional Bell companies, such as U.S. West, Bell Atlantic and Southwestern Bell, and the national long distance companies, such as AT&T and Sprint. The enhanced competition has driven the price of cellular service down to the point where it is affordable to a large segment of the population.
Wireless subscribers use a wide variety of wireless devices, including cellular phones, personal communication services (PCS) devices, and wireless modem-equipped personal computer (PCs), among others. The large number of subscribers and the many applications for wireless communications have created a heavy subscriber demand for RF bandwidth. To maximize usage of the available bandwidth, a number of multiple access technologies have been implemented to allow more than one subscriber to communicate simultaneously with each base transceiver station (BTS) in a wireless system. These multiple access technologies include time division multiple access (TDMA), frequency division multiple access (FDMA), and code division multiple access (CDMA). These technologies assign each system subscriber to a specific traffic channel that transmits and receives subscriber voice/data signals via a selected time slot, a selected frequency, a selected unique code, or a combination thereof.
To further maximize frequency reuse, wireless carriers frequently implement smaller cells, sometimes referred to as “microcells” or “picocells.” The base transceiver station in a microcell (or picocell) broadcasts at relatively lower power over a smaller geographical regions, so that cells may be packed tighter together. This requires a greater amount of infrastructure equipment, but a greater number of subscribers to be serviced by the entire wireless network.
A base transceiver station in a wireless network contains numerous standard-commodity digital processors, such as the MPC860 PowerQUICC™ from Motorola, that process the calls being handled by the base transceiver station. The digital processors establish, maintain, and terminate wireless connections between mobile stations (i.e., cell phones, PCS devices, wireless PCs, pagers, etc.) used by subscribers and the wireless network. The digital processors contain hardware communication ports that are used in the process of transmitting and receiving data in the base transceiver station. The communication ports are in turn controlled by internal registers, called buffer descriptors, which set up the communication ports. These registers form a buffer descriptor array that may be used to store status and control information about the communication ports and the data being communicated.
The status and control information is used for both the transmission and the reception of data. This status and control information includes 1) the starting address of the data buffer holding the needed data, 2) the length of the data in the data buffer and 3) bits that may be used to activate and deactivate the digital processor or to indicate certain conditions, including errors.
However, the architecture of digital processors provide only a relatively limited number of registers to be used as buffer descriptors. Since the buffer descriptors are used to control communication ports, and the communication ports control the number of calls handled by the base transceiver station, any limitation on the size of the buffer descriptor array also limits the throughput of the base transceiver station. If the transmitter buffer descriptors of a digital processor are filled when additional data packets are available for processing and transmission, the additional packet processing must wait until a transmitter buffer descriptor becomes available to store them. On the receiver side, if the receiver buffer descriptors are waiting to transfer data to the transmitter buffer descriptors while the transmitter buffer descriptors are unavailable, then incoming data to the receiver is lost because there are no registers in which to store the newly received data.
There is therefore a need in the art for improved transceiver systems for use in wireless networks. In particular, there is a need for communications systems that are not limited by the hardware design of commercially available communications processors. More particularly, there is a need for communications systems that are able to expand the call handling capabilities of communications processors.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a communications device, a transceiver controller that uses hardware buffer descriptors and a virtual array of buffer descriptors to control the communication ports of a communication processor. The virtual array of buffer descriptors is a data structure comprising data fields that is similar to the hardware buffer descriptors of the communication processor and provides “just in time” storage of control and status information used by the communication ports of the communication processor to transmit and receive data. An interrupt controller detects a full condition in the hardware receiver buffer descriptors and loads the contents of the hardware receiver buffer descriptors into a receiver virtual array of buffer descriptors with as many buffer descriptors as needed. After the receiver virtual array of buffer descriptors is loaded, the hardware receiver buffer descriptor is initialized to received more data.
With respect to transmitter functions, the communication processor, under control of application software, takes outbound data from a receiver port or from other data sources in, or connected to, the transceiver controller and fills the transmitter virtual array of buffer descriptors and sets the proper control bits. An interrupt controller detects an emptiness condition, or is triggered by a timer, and moves the contents of the transmitter virtual array of buffer descriptors to the hardware transmitter buffer descriptors. The transmitter virtual array of buffer descriptors is cleared and control bits are reset to allow incoming data to be stored in the transmitter virtual array of buffer descriptors.
Accordingly, in one embodiment of the present invention, there is provided, for use in a communications network, a communications controller capable of transmitting outbound data to a receiving node and receiving incoming data from a transmitting node comprising: 1) a processor comprising: a) a plurality of transmit buffer descriptors, each of the plurality of transmit buffer descriptors comprising at least one register capable of storing transmit configuration information used by the processor to control a transmission of the outbound data; and b) a plurality of receive buffer descriptors, each of the plurality of receive buffer descriptors comprising at least one register capable of storing receive configuration information used by the processor to control a reception of the incoming data; and 2) a memory coupled to the processor and capable of storing the transmit configuration information in a virtual transmit buffer descriptors array and storing the receive configuration information in a virtual receive buffer descriptors array, wherein the processor transfers the receive configuration information from at least one of the plurality of receive buffer descriptors to the virtual receive buffer descriptors array when the plurality of receive buffer descriptors are full.
According to another embodiment of the present invention, the processor transfers the transmit configuration information from the virtual transmit buffer d
Corsaro Nick
Han John C.
Hunter Daniel S.
Samsung Electronics Co,. Ltd.
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