Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
2001-01-08
2003-08-12
Siek, Vuthe (Department: 2825)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
C716S030000, C716S030000, C712S214000
Reexamination Certificate
active
06606703
ABSTRACT:
This application is based on applications Nos. H9-234354 and H10-095645 filed in Japan, the content of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor and an instruction conversion apparatus, and in particular to a technique for reducing the number of types of instructions and the processor hardware scale when conditional instructions are used.
2. Related Art
In recent years, improvements in performance and processing speed of appliances using embedded microprocessors have led to an in creasing demand for microprocessors (hereinafter simply referred to as “processors”) with high processing capability.
A basic technique for increasing processing speed is a pipeline processing.
In the pipeline processing, the processing of each instruction is divided into a plurality of processing units (pipeline stages) and pipeline stages for different instructions are executed in parallel so that processing speed is improved.
The pipeline processing is disturbed, however, (pipeline stalls occur) when executing a branch, reducing the execution performance of the pipelines to below an ideal level. This phenomenon is called a “branch hazard”.
Recent processors use conditional instructions instead of branch instructions to reduce branch hazards to improve their processing capabilities. The conditional instructions are, for instance, described in detail in “The ARM RISC Chip-A Programmer's Guide”, Addison-Wesly Publishing Company Inc.
FIG. 30
shows an instruction sequence including a conventional conditional transfer instruction. In
FIG. 30
, each of the legends “r0”, “r1”, and “r2” represents a register. The instruction
3001
is a transfer instruction for transferring the value “1” to the register “r0”. The instruction
3002
is a comparison instruction for comparing the values of the registers “r1” and “r2” and setting various flags to indicate the comparison result. The instruction
3003
is a conditional transfer instruction for referring to the flags and, when the values compared by the instruction
3002
are equal, transferring the value “0” to the register “r0”.
FIG. 31
shows a list of conventional conditional transfer instructions
3101
. This list includes six types of conditional transfer instructions
3101
. The condition
3102
is a sign indicating a condition specified by each conditional transfer instruction. When the operation objects “a” and “b” are compared by a comparison instruction, the condition is one of the following cases: “a” and “b” are equal; “a” and “b” are not equal; “a” is greater than “b”; “a” is greater than or equal to “b”; “a” is smaller than “b”; and “a” is smaller than or equal to “b”. Each conditional transfer instruction is executed when its condition is satisfied.
FIG. 32
shows conventional instructions, such as comparison instructions (CMP instructions), conditional addition instructions for performing addition when their conditions are satisfied, conditional transfer instructions for performing transfer when their conditions are satisfied, and conditional branch instructions for performing branch when their conditions are satisfied. In these instructions, last two characters of the operation code of each instruction in mnemonic code specify the condition.
The number of types of conditions of each conditional instruction and each conditional branch instruction shown in
FIG. 32
is ten because the conditions shown in
FIG. 32
include conditions for data with signs, in addition to the conditions shown in FIG.
31
.
Accordingly, the total number of types of instructions including a comparison instruction, conditional instructions for each of two operations (conditional transfer instructions and conditional addition instructions), and conditional branch instructions is thirty-one. Here, if there are A operations of conditional instructions, the total number is represented as 11+(10×A).
There are also conditional instructions whose number of types is reduced. These conditional instructions are described in detail in “Hitachi Single Chip RISC Microcomputer SH7000/SH7600 Series Programming Manual”, Hitachi, Ltd., p57-p58, p69-p70, and p75-p78.
FIG. 33
shows comparison instructions, conditional addition instructions, and conditional branch instructions where the number of instruction types is reduced.
Here, the conditional instructions and the conditional branch instructions shown in
FIG. 33
use only two types of conditions, that is, a conditional flag is set or is reset. Therefore,
FIG. 33
shows two types of conditional addition instructions, two types of conditional transfer instructions, two types of conditional branch instructions, and five types of comparison instructions for setting or resetting the conditional flag.
Accordingly, the total number of types of instructions including comparison instructions, conditional instructions for each of two operations, and conditional branch instructions is eleven. Here, if there are A types of operations of conditional instructions, the total number of types of instructions including comparison instructions, conditional instructions for each operation, and conditional branch instructions is represented as 7+(2×A).
Processors performing pipeline processing need to use more types of conditional instructions to reduce branch hazards as much as possible.
However, because each instruction executed by a processor has a fixed-length bit pattern, the number of types of instructions which the processor can use is limited.
Accordingly, the number of types of conditional instructions which the processor can use is limited. As the number of types of instructions increases, more hardware is required to decode instructions, increasing the cost of the processor.
SUMMARY OF THE INVENTION
In view of the stated problems, the object of the present invention is to provide an instruction conversion apparatus which reduces the number of types of instructions and a processor whose hardware scale is reduced, when conditional instructions are used.
To achieve the above object, the processor of the present invention which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.
With the stated construction, the processor of the present invention uses an instruction set including only conditional instructions specifying one out of a pair of exclusive conditions, not including conditional instructions specifying the other of the pair. Therefore, the number of types of conditional instructions is reduced, in comparison with a conventional processor.
Accordingly, hardware scale of an instruction decoder can be reduced. Also, when the number of types of instructions is limited, the processor o
Heishi Taketo
Higaki Nobuo
Miyaji Shinya
Odani Kensuke
Suzuki Masato
Matsushita Electric - Industrial Co., Ltd.
Siek Vuthe
Tat Binh C.
LandOfFree
Processor using less hardware and instruction conversion... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor using less hardware and instruction conversion..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor using less hardware and instruction conversion... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3076459