Processor to memory interface logic for use in a computer system

Details Processor to memory interface logic for use in a computer system Processor to memory interface logic for use in a computer system

1997-04-25

1999-08-03

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

36523002, 36523008, G06F 1202

Patent

active

059338598

ABSTRACT:
Interface logic for interfacing a processor to a memory unit is disclosed. The interface logic in one embodiment of the present invention uses a single port to both receive an address from the processor and drive a multiplexed address to the memory unit. By causing the processor to relinquish control of the address bus, the interface logic can drive an address over the same lines used by the processor to communicate the address to the interface logic. This procedure eliminates the need for two ports, and therefore reduces the pin count of the interface logic. For example, in a non-paging implementation, an interface bus is connected to a row portion of the address bus. The processor drives the row address over the row portion of the address bus and thereby also over the interface bus to the memory unit. The interface logic (1) stores the column address that is placed on the address bus by the processor, (2) causes the processor to relinquish control of the address bus after the processor has driven the row address to the memory unit, and then (3) drives the column address over the row portion of the address bus and thereby also over the interface bus to the memory unit address port.

REFERENCES:
patent: 5124560 (1992-06-01), Fueki
patent: 5157692 (1992-10-01), Horie et al.
patent: 5175854 (1992-12-01), Cheung et al.
patent: 5191581 (1993-03-01), Woodbury et al.
patent: 5305443 (1994-04-01), Franzo
patent: 5526513 (1996-06-01), Cerutti

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