Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-04-10
2007-04-10
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S028000, C712S227000, C717S124000
Reexamination Certificate
active
10670233
ABSTRACT:
A processor system, comprising: a first program storage which stores a first program; a second program storage which stores a second program; a program counter which outputs execution addresses of said first and second programs; a first address storage which stores a first address in said first program; a second address storage which stores a second address in said second program; a comparator which compares whether or not said program counter coincides with said first address; an address changing unit which changes said program counter to said second address, when it is determined to have coincided by said comparator; and a data bus which updates said first address stored in said first address storage and said second address stored in said second address storage. A arithmetic processing method, comprising: outputting from a program counter execution addresses of a first program stored in a first program storage and a second program stored in a second program storage; determining whether or not said program counter coincides with a first address in said first program stored in said first address storage; and changing said program counter into a second address in said second program stored in said second address storage, when it is determined to have coincided.
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Beausoliel Robert
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Puente Emerson
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