Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2004-10-25
2009-11-24
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Reexamination Certificate
active
07624295
ABSTRACT:
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.
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Do/loop statement by Powerbasic.com.
While/When statement by Powerbasic.com.
Japanese Notice of Reasons for Rejection, w/ English translation thereof, issued in Japanese Patent Application No. JP 2003-366042 dated Mar. 24, 2009.
Taketoshi Osamu
Tanaka Isao
Wada Toru
Lee Thomas
McDermott Will & Emery LLP
Panasonic Corporation
Rehman Mohammed H
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